Lab Result: An AI Model Designs a Circuit That Reroutes Its Own Logic After Damage

A topology-masked Transformer has learned to configure the Boolean logic gates of a digital circuit so that, when part of the circuit is damaged, the surrounding logic re-routes the function without external help. The result is reported in a 7 May 2026 arXiv preprint by researchers at ITU Copenhagen, Imperial College London, and Google's Paradigms of Intelligence Team, and it is, for now, a simulation, not a fabricated or deployed chip.

The paper calls the construction a "Self-Organising Digital Circuit." Under the hood, a Transformer with shared weights is applied recurrently across a circuit graph, using a binary wiring mask so each gate only sees the connections it is physically wired to. The model's job is to write the lookup tables that define what each Boolean gate does. The authors train it offline with backpropagation through time, using a continuous relaxation of the lookup tables so gradients flow; at deployment, only local forward passes are needed. No differentiable hardware is required to run the trained policy, which is what matters for embedded or radiation-exposed environments where a Python training loop cannot run on the device itself.

The result the paper leans on is recovery after damage. On soft-error fault patterns the model was not exposed to during training, including damage five times larger than anything it saw during training, the paper reports more than 99.99% accuracy recovery, with edit size, meaning how much of the circuit the policy has to rewrite, staying roughly constant as the perturbation grows. The same trained policy also generalises across circuit scales, transferring from 264-node training graphs to graphs of 450 or more nodes with accuracy that improves rather than degrades on the wider topology.

The work extends Neural Cellular Automata, the paradigm in which a local rule is applied repeatedly to update every cell in a grid so that a damaged pattern regrows from a seed, from regenerating images to configuring functional logic. Co-author Alexander Mordvintsev co-authored the original NCA paper, and the lineage shows. The authors pitch the result as an alternative to static fault-tolerance: error-correcting codes and modular redundancy protect circuits by adding extra gates and voters, and that cost is paid in silicon area and power at design time. A self-reconfiguring circuit pays the cost only when damage actually occurs, which is the relevant regime for a satellite that cannot be serviced, an undersea cable, or a remote sensor.

The caveats are the paper's own. It is an arXiv preprint, not peer-reviewed. The 99.99% figure is author-reported on a specific simulation fault model (soft errors in a Boolean circuit), and the policy has not been demonstrated on real silicon. The authors position the work as an extension of the NCA pattern-generation paradigm, not a replacement for established hardware redundancy. "Previously unseen" refers to the fault types in the test set, not every failure mode a chip might face in orbit.

The paper does not claim to ship a self-healing chip; the open question is whether a learned, local-update rule for Boolean gates is a useful design primitive at all, and the open code at github.com/GabrielBena/boolean_nca_cc lets independent groups test that against their own fault models. The next milestone to watch is whether the same training pipeline holds up on a wider fault taxonomy (timing errors, bridging faults, ageing degradation) rather than the soft-error slice the paper reports on.