The '2 nanometer' chip node is the most advanced commercial generation, dominated by TSMC, and price competition is the lever Rapidus picked: the same one Samsung and Intel Foundry have already pulled.
Rapidus CEO Atsuyoshi Koike this week put a number on Japan's challenge to the world's leading chipmaker: ¥3 million to ¥3.5 million (about $18,550 to $21,635) per wafer for 2-nanometer silicon, with first volume production targeted for 2027. That is a deliberate undercut of the rumored ~$30,000 per wafer TSMC is reported to charge for its competing N2 process. Whether the lower wafer price translates into customer orders depends on what sits beside the wafer, not the wafer itself.
The "2nm" label is shorthand for the most advanced commercial chipmaking generation in production, the transistors behind flagship phone processors, AI training chips, and data-center CPUs. The foundry business at that generation is, for practical purposes, one company: Taiwan Semiconductor Manufacturing Company (TSMC), which fabricates the bulk of advanced silicon for Apple, Nvidia, AMD, and Qualcomm and has widened its share with each node shrink for more than a decade. Rapidus is the Japanese government's flagship bet to field a second leading-edge supplier, with its first plant in Chitose, Hokkaido. Koike has acknowledged that final pricing will move with the yen-dollar exchange rate, widening the gap between announcement and invoice.
Rapidus has said its high-volume manufacturing start lands in 2027, with meaningful production scaling into 2028. By that point, TSMC is slated to be ramping N2P, a refined 2nm-class node, and A16, its 1.6nm-class successor built on a backside power-delivery architecture called Super Power Rail that moves power routing to the back of the die. Reaching meaningful volume in 2028 places Rapidus behind TSMC's second 2nm-class generation, not its first.
Leading-edge foundries sell a system, and TSMC's Open Innovation Platform (OIP) bundles the EDA (electronic design automation) toolchains engineers use to lay out circuits, libraries of silicon-proven intellectual-property blocks that drop into a design, partnerships with the design houses that use those tools every day, and advanced packaging options such as CoWoS (chip-on-wafer-on-substrate) that let customers combine multiple dies into one package. A cheaper wafer price does not buy any of these dependencies.
Samsung and Intel Foundry have already tried this pricing approach at this generation. Samsung's SF2 process has been reported in roughly the same $20,000-per-wafer band Rapidus is now targeting, and Intel Foundry has priced its 18A node to win outside customers. Neither has taken meaningful leading-edge share from TSMC. The reason tracks to ecosystem, not wafer price: design teams porting a chip between foundries face re-validation of every IP block, every timing-closure pass, every packaging flow. The switch cost is measured in quarters of engineering time, which is why the price gap has stayed visible while the share gap has not moved.
Rapidus has not shipped in volume. Koike's pricing posture is the first concrete anchor, and the next milestones are dated and falsifiable: first customer wafers from the Chitose pilot line, the yield curve on Rapidus's gate-all-around (GAA) transistors at the 2nm node, and the first external tape-out (the moment a customer commits a finished chip design to a foundry) for a real product. A 2nm wafer contract signed at ¥3 million to ¥3.5 million before TSMC's A16 ramps into volume is the concrete test.