Intel's 18A-P Process Targets AI Accelerators With 9% More Performance or 18% Lower Power

Intel detailed a mid-life performance variant of its 18A chipmaking recipe at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, with Semiconductor Engineering reporting the foundry's first "Power Boost" option in the 18A family. The new variant, called 18A-P, delivers more than 9% higher performance at the same power, or over 18% lower power at the same performance, versus the base 18A node.

The gains come from three layers: a new RibbonFET gate-all-around transistor option with Power Boost and strain engineering, transistor and interconnect refinements, and design-technology co-optimization. The top-end device pairs Power Boost with a dual-contact architecture and ultra-low-resistance contacts, raising drive current so chips can run faster at matched capacitance.

18A-P is fully design-rule compatible with 18A and keeps the same SRAM cell and minimum operating voltage, so customers can reuse existing IP, libraries, and design flows rather than re-spin for a new node.

The numbers are Intel's own, carried in the company's VLSI 2026 paper and tipsheet, not independently benchmarked. The source is silent on head-to-head comparisons with TSMC's N2 or A16, on customer adoption, and on volume-manufacturing timing. Whether the dial actually moves the needle for AI fleet power budgets will be settled by silicon in customer hands, not by a conference paper.