Intel's reported 14A2, a follow on to its existing 14A chipmaking process, would route electricity through both faces of the silicon, a once exotic technique now central to the chipmaking race.
Intel is reportedly weighing a follow-on to its 14A chipmaking process that would feed electricity into the silicon from both the front and the back of the die at the same time, a refinement aimed at keeping pace with TSMC's A14 node and Samsung's 1.4nm offering as the industry's "nanometer race" gives way to a contest over power delivery. The reporting traces to Korean trade outlet ETNews via TrendForce and was picked up by WCCFTech.
The design under consideration, labeled "14A2" in that coverage, builds on the backside power delivery Intel has already built into its baseline 14A node. In a backside scheme, the power rails that feed each transistor run through the underside of the wafer instead of competing for space with signal wiring on top. The reported 14A2 twist is to add a second set of front-side rails back on top, turning backside delivery into a fully dual-sided system. TrendForce and a separate WCCFTech analysis frame the move as Intel's response to a problem all three leading-edge foundries now share.
The problem, in plain terms, is that at the metal pitches the industry is now targeting, roughly 21 nanometers between the wires that connect transistors, front-side-only power delivery starts to hit physical walls. Resistance rises, voltage drops across the chip, and the routing that carries current crowds out the routing that carries data. Routing power up from underneath frees the top layers for signals, and layering front-side rails back on lets the foundry push more current through without paying for it in performance. WCCFTech describes the choice as a "power delivery rethink" forced by interconnect scaling.
That tradeoff is not unique to Intel. TSMC has already said its A14 node, currently ramping toward 2027 production, will use a backside power delivery network of its own design. Samsung has signaled its 1.4nm node, targeting mass production around 2029, will follow suit. A Tom's Hardware roadmap analysis lays out how each company plans to get there. The convergence is the story: three competing foundries, three different brand names, the same underlying engineering problem.
For Intel, the 14A family carries extra commercial weight. It is the first manufacturing process the company has explicitly pitched to outside customers as a foundry offering, a deliberate attempt to win chip designs away from the Taiwan- and Korea-dominated supply chain. HotHardware reports Intel is positioning itself for "major foundry deals" on the strength of 14A, with the node's perf-per-watt and density story doing the selling. A rumored 14A2 refinement, even one Intel never confirms, would be Intel's answer to a question TSMC and Samsung are also still answering: how do you keep density and performance per watt climbing when the old lever, calling the next node a smaller number of nanometers, has stopped meaning anything physical? "1.4nm" is a marketing label, not a measurement. The architectural decisions underneath it are what will determine which foundry ends up building the AI accelerators and high-performance processors of the late 2020s.
The 14A2 reporting is based on ETNews and has not been confirmed by Intel. The TSMC 2027 and Samsung 2029 dates are industry-reported roadmap estimates, not contractual commitments. Backside power delivery itself is no longer speculative: Intel, TSMC, and Samsung have all presented versions of the technique at IEDM and at Intel's Foundry Direct Connect events, and the engineering tradeoffs are well understood. What is not yet known is whether a dual-sided scheme offers enough extra density or efficiency to justify the added process complexity, or whether it remains an Intel-only design point.
The next concrete trigger is whether Intel, or any of the foundry customers it has been courting for 14A, comments on the 14A2 plan at Intel's next Foundry Direct Connect or at IEDM this winter.