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Optane was Intel's discontinued memory chip built for the write heavy, latency sensitive workloads AI now runs every day, and its absence is one reason DRAM prices are climbing again.
AI's RAM squeeze is a missing-middle problem. The chip that fit the missing middle was Optane, and Intel discontinued it before AI demand arrived.
DRAM is the fastest tier, volatile, expensive, and now squeezed. NAND flash, the cheap non-volatile tier below, is too slow and burns out under AI's constant writes. The tier in between was Optane, and Intel ended it years before that workload became the dominant reason to buy servers.
Optane was Intel's line of memory and storage products built on 3D XPoint, a non-volatile memory media Intel co-developed with Micron and unveiled in 2015. Two product shapes mattered: Optane SSDs, which sat on the PCIe bus, and Optane persistent memory DIMMs, which slotted into the memory channels alongside regular DRAM. Both targeted the gap between NAND and DRAM on latency, endurance, and byte-addressability.
The exit timeline is consistent across Tom's Hardware and Intel's own support documentation: Micron left 3D XPoint in 2021, Intel followed in July 2022, with the P5810X and P5811X SSDs as the last products later that year. Final 200-series Optane DIMM shipments ran through late 2025.
The numbers tell why the gap was real. The P5800X SSD spec sheet lists sub-10-microsecond latency, 100 drive writes per day of endurance, and a 2-million-hour mean time between failures. Optane DIMMs sat at roughly 350 nanoseconds of latency and shipped at capacities up to 512 GB per module, against 128 GB for the DDR4 modules common in that era. Latency, endurance, and capacity: each lines up with what AI workloads now ask of memory.
The workload in question is the KV cache. When a large language model generates a response, it keeps a working table of past tokens close to the chip, a key-value cache that grows with the length of the conversation. The Register cites the same use case: a single 64,000-token sequence on a DeepSeek R1-style model can occupy roughly 4 GB of GPU memory. As prompts and context windows stretch into hundreds of thousands of tokens, that working set blows past what fits on a single GPU's HBM and spills over to whatever sits beside it. NAND wears out under that write pattern. DRAM costs too much to dedicate to the spillover. Optane was built for it.
The cost of not having the tier shows up in build budgets. TrendForce reports NVIDIA has halved the SOCAMM capacity on the next-generation Vera Rubin platform, from 192 GB to 96 GB per module, because memory is approaching 29 percent of the system's bill of materials, against an estimated $2.1 million (USD) price for a fully built VR200. HBM4 is forecast at roughly $53 per gigabyte (USD) by 2027, per a Bernstein note circulated through Wccftech and TrendForce.
The honest counter is the one Intel's accountants reached in 2022. 3D XPoint's per-bit density never caught up with NAND, so the cost per gigabyte stayed too high for commodity use. Micron left first, and Intel's product line could not stand on its own. A chip that would have been the right answer in 2026 was the wrong answer in 2022, and the 2022 exit set the 2026 squeeze in motion.
What replaces the missing middle is still being assembled. CXL-attached memory pools DRAM across servers, HBM stacks keep adding layers, and NAND controllers learn to spread write load. Each closes part of the gap Optane would have filled. None is a drop-in.
The cleanest move for AI buyers is to ask vendors one question on every procurement: which tier holds the KV cache, and what does that tier cost per gigabyte and per write? If the answer keeps narrowing to HBM only or DRAM only, the missing middle is being paid for somewhere else in the budget, and the next price cycle will surface it.