Intel has run 3 of every 4 High-NA EUV wafers ever processed, and the million-wafer count isn't all shipping chips

Intel has now run more than a million 300mm wafers on ASML's High-NA EUV scanners, the most advanced chipmaking tools in commercial use and the only lithography systems currently capable of patterning the sub-2nm process nodes where AI accelerators and flagship PC chips are headed. The figure puts Intel at roughly three-quarters of every wafer ASML's High-NA fleet has ever exposed, and it lands in the same week that Nvidia and the US government hold equity stakes in Intel's foundry and the company's stock is up nearly 155% year-to-date. The honest question is not whether Intel hit a million; it did. The question is what kind of million it is.

The joint Intel and ASML disclosure, delivered at the SPIE Photomask Technology and EUV Lithography conference in Monterey, attributes the milestone to a single machine category: ASML's EXE-class High-NA EUV scanners, of which ten are running at four customers and three more are shipping or being installed. Per ASML's Greet Storms, the company's head of High-NA product management, the installed EXE base has collectively exposed more than 1.35 million wafers across research, tool certification, and high-volume manufacturing. Intel's slice of that total, the roughly 74% share, is what Intel is calling a milestone, and what its competitors will read as either a structural lead or a tall tale depending on how the R&D mix breaks down.

That mix is the part of the press release that did not get the headlines. Intel and ASML both note that the company's million-wafer figure bundles three things: internal R&D projects, the long certification runs each new scanner requires before it can pattern production silicon, and the volume manufacturing of Core Ultra Series 3 CPUs (codenamed Panther Lake) on Intel 18A. A reader who hears "one million wafers" and pictures a million shipping chips is reading the wrong number. A more accurate read is that Intel is by a wide margin the foundry with the most hours of High-NA EUV exposure on its books, but the share of that exposure that turns into HVM-grade silicon is not in the public figure.

High-NA EUV is the gate to sub-2nm: the resolution improvement over today's low-NA EUV systems is what lets a foundry draw the gate geometries that 2nm-class logic and the next generation of high-bandwidth memory require, with fewer multi-patterning steps and lower defectivity. ASML's four High-NA customers today are Intel, TSMC, Samsung, and SK Hynix, and the spread of installed tools across those four is the cleanest single proxy for who is actually running the next-generation lithography at volume. Intel's roughly 74% of ASML's reported 1.35M total is not a node-leadership claim; it is a tool-share claim, and the two should not be conflated.

Intel's stake in claiming tool-share is concrete. The company is rebuilding itself as a contract chipmaker, a foundry for outside customers, and the foundry thesis is what the Nvidia and US government equity positions are pricing. A foundry that runs the most advanced lithography tool the most hours has a credible answer to the hardest customer question, which is whether Intel 18A and its successors can deliver competitive yields on advanced nodes. A foundry that runs the tool mostly on its own R&D and certification has a less convincing answer, regardless of the headline number.

As of the SPIE disclosure, ASML's ten-system footprint is split across four customers, with three more EXE systems shipping or being installed. If the next wave of installs skews toward TSMC or Samsung over the next two quarters, Intel's tool-share lead will compress even if its absolute wafer count keeps rising. Independent confirmation of the R&D-versus-production split inside Intel's million-wafer figure would settle whether the lead is structural or partly a measurement artifact. Other outlets covering the disclosure have not yet published an independent third-party read of the split. The first external customer tape-out on Intel 18A, expected in 2027, will be the harder test than any wafer count. Today, Intel has the most hours on the most advanced tool, and the foundry race is being decided at the lithography layer.