VLSI is the chip industry's leading annual symposium for advanced silicon research, and Intel's 18A and 18A P chipmaking processes show real measured gains from routing power to the back of the wafer, but the customer tape outs — production ready chip designs — that would prove…
Intel Foundry used the 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits to argue that backside power delivery, the practice of routing power wiring to the back of the wafer while leaving signal wiring on the front, is the architectural unlock behind its 18A and 18A-P processes. The engineering results Intel published are real, but they are also Intel's own measurements on Intel test vehicles, and the company has not yet named the external customers whose production tape-outs would mark the technology as foundry-validated.
In a sponsored recap on Semiconductor Engineering, Intel frames six VLSI 2026 papers as a unified platform story. The throughline is the same in each: moving power off the front-side metal stack removes a long-standing bottleneck in advanced-node design and gives engineers a new set of tradeoffs to work with.
The clearest datapoint is in a paper on CPU cores using gate-all-around (GAA) transistors with backside power. Intel reports roughly 30% higher frequency at around 0.5 V compared with a FinFET baseline. Low-voltage operation is the part of the curve that matters most for mobile chips, AI-edge inference accelerators, and any battery-powered workload where every millivolt of headroom translates into longer runtime.
Backside power also changes the physics of power delivery itself. A separate backside power delivery on advanced nodes paper reports an 11% area reduction in routed blocks and a peak dynamic voltage droop under 10 mV, versus more than 90 mV on Intel 3 with conventional frontside power. Lower droop means cleaner voltage at the transistor, which Intel says translates to a 5 to 6% frequency uplift or up to 15% power reduction at constant performance.
The 18A-P variant, Intel 18A-P with Power Boost, is now in risk production, and Intel stresses that it is design-rule compatible with the original 18A node. That compatibility matters: it lets customers who already targeted 18A carry their designs forward without a full re-spin. On an iso-power test, which holds power constant while measuring speed, of a standard ARM core sub-block, Intel reports a 9% performance gain at 0.75 V and a corresponding 18% power reduction at constant performance compared with 18A. The Power Boost dual-contact architecture lands separate frontside and direct-backside contacts to the PowerVia backside power rail, improving NMOS and PMOS transistor resistance, and pairs that with a 20 to 40% thermal resistance improvement and updated EDA (chip design automation) workflows.
There is a quieter cost story in the package. Because the frontside metal stack no longer has to carry power, Intel says customers can use more cost-effective 32 nm metal pitches on 18A and 18A-P, with fewer masks and manufacturing steps. Routed-design area is the lever most chip designers reach for when they need to hit a cost target, and an 11% area win on routed blocks is a real number on a die cost model.
The remaining three papers are forward-looking. 300 mm GaN-on-Si digital logic, developed with the University of California San Diego, hit a 6.2 attojoule-per-stage power-delay product, a 1,000× improvement over prior work and, Intel says, the largest-scale integrated logic ever demonstrated on gallium nitride on silicon. The other two papers present a scaled complementary FET (CFET) process and a subtractive ruthenium interconnect scheme with air gaps for tight metal pitches. Each is a research result, not a product, and each points to a different post-18A decision Intel is keeping on the table.
The framing that matters for readers outside the foundry beat is what Intel's data does and does not show. The numbers are all Intel-measured on Intel's own test vehicles: there is no independent third-party benchmark, no customer tape-out announcement, and no disclosed yield or defect-density data. Treating six VLSI papers as a foundry-versus-foundry verdict would be premature. Treating them as a research-to-production progress report is closer to the mark. Backside power is now in risk production at 18A-P, and the next real test is which outside customers ship silicon on it at volume, and whether the gains hold up under independent characterization.