Instead of HBM or leading-edge nodes, Dongfang Suoxin (东方算芯) 3D-stacks logic and DRAM in 14nm DF1000 to attack inference's data-movement cost

On July 13 in Shanghai, 东方算芯 (Dongfang Suoxin) launched the DF1000, billed as the first commercial software-defined near-memory AI chip in China. The launch is the first explicit product bet that process node and HBM access are not the only competitive axes that matter for domestic AI silicon, and it lands in the middle of the broader industry pivot from training to inference.

The reason architecture and packaging are doing the work is a shift in which cost dominates. Pre-training is dominated by large matrix multiplications on big batches, so the chip spends most of its time computing. Inference, especially the decode phase that produces one token at a time, is dominated by repeatedly reading model weights and the working key-value cache from memory. The bottleneck moved from arithmetic to data movement.

That shift is what makes 近存计算 (near-memory computing) interesting. The idea is to place compute logic physically close to memory so each weight read costs less energy and less time. 东方算芯 pairs that with a 软件定义芯片 (software-defined chip) design, where hardware resources are reorganized per workload rather than fixed at design time, and 粗粒度计算 (coarse-grained compute) blocks that can be rewired on the fly.

Standard AI accelerators pair logic dies with 高带宽存储器 (HBM, or high-bandwidth memory), stacks of DRAM connected through a silicon interposer. HBM is controlled by a small group of suppliers and is currently capacity-constrained. 东方算芯's response is 3D混合键合 (3D hybrid bonding), stacking logic wafers directly on DRAM wafers at the wafer level, bypassing the HBM packaging path entirely.

The DF1000 ships in a 14nm process and reports 520 TFLOPS at BF16 (bfloat16, a 16-bit floating-point format common in AI training and inference) per card, with 6.4 TB/s of memory bandwidth. The company frames this against HBM-equipped peers and claims roughly 5x the bandwidth at the same memory capacity, a baseline the launch materials call out explicitly. Those numbers come from 东方算芯's own press materials and the July 13 launch coverage at Leiphone. No third-party MLPerf-class benchmark is visible yet.

The card is one tier of a four-level stack: the 巅峯 DF1000 OAM2.0 card, the 擎元 QY100 8-card server, the 拓域 TY64 64-card supernode rated at 33 PFLOPS@BF16, and the 慧算 HS128 cluster of 128 cards. The company demonstrated the 128-card configuration in stable, full-function operation, per the 2026 WAIC SAIL Award coverage by 智东西. The 33-petaflops supernode figure and the 128-card stability claim both come from vendor demonstrations at the 2026 WAIC SAIL Award coverage by 智东西, not independent validation. The DF1000 was named to the 2026 WAIC SAIL Award (卓越人工智能引领者奖) TOP30 list.

东方算芯 ships CAAP, a full software stack covering compiler, runtime, operator library, collective-communication library, distributed training framework, and a one-stop toolchain. The company claims compatibility with mainstream deep-learning frameworks and 万卡级 (10,000-card) cluster scale. Independent confirmation of framework porting and developer uptake is not yet public.

东方算芯 was founded in May 2024 in Shanghai's Zhangjiang high-tech zone and is led by 魏少军 (Wei Shaojun). Vice president 郭炜 has been the company's technical voice on the architecture in launch coverage. The technical lineage traces to roughly two decades of reconfigurable-computing research at the Tsinghua microelectronics institute.

At the launch, two industry voices set out the rationale. Hong Kong Academy of Engineering fellow 郑光廷 cited the energy constraint, that data movement now dominates inference power budgets, as the reason near-memory matters. 赵超, executive vice president of the Beijing Superstring Memory Research Institute, framed the same shift as a Von Neumann bottleneck: compute and memory have been separated for seventy years, and AI workloads are the first to make that separation economically untenable. Both are speaker-anchored context, not independent performance validation, and the trade press coverage at eefocus reports the same framing.

The 14nm node is the bottleneck the whole thesis rests on. The launch materials do not name the foundry; trade press has inferred SMIC, but that is inference, not disclosure. The 3D hybrid bonding supply chain partner is not named in the launch coverage, so a fully domestic OSAT supply chain is a working assumption rather than a confirmed claim. The founder interview at Sina Finance and QQ News carry the corporate valuation, around 12.3 billion RMB (roughly $1.7 billion at current rates), but do not resolve the foundry question.

The bet will be tested on four fronts. First, third-party benchmarks on the 520 TFLOPS and 6.4 TB/s claims, ideally MLPerf results. Second, sustained multi-day cluster runs at 128 cards rather than single demos. Third, named design-win customers beyond the launch event. Fourth, CAAP-stack ecosystem uptake: frameworks ported, operators contributed, developers publishing. The company's own roadmap points to a second-generation chip in mass production by the fourth quarter of 2027, per the Leiphone launch coverage, which would be the first concrete checkpoint.

DF1000 is a concrete architectural response to a supply-chain constraint. Whether the response carries the company into the inference market depends on benchmarks, customers, and software that the July 13 launch did not yet supply.