India's $15B chip push: more players, smaller per-fab subsidy

India notified the second phase of its national semiconductor programme on Monday, a ₹1.27 lakh crore (about $15 billion) scheme that widens who can claim chip subsidies and lowers what the largest silicon fabs can claim, dropping per-project capex support from 50% to 40%.

The new framework, Semicon 2.0, extends eligibility to chip-design startups, micro and small manufacturers, packaging companies, materials and equipment makers, display fabs, and research and training institutions. That is a real expansion from the first phase, which was built around a small set of marquee silicon fabs. The change is the government's first structured move into the design and packaging layers, not just the wafer-fab layer.

The broader access comes with a smaller per-project check. Support for silicon-wafer fabs drops from 50% of eligible capital expenditure under Semicon 1.0 to 40% under Semicon 2.0, according to the BusinessToday summary of the gazette notification. The eligibility floor for those mega-fabs is also stiff: a minimum ₹20,000 crore (about $2.4 billion) investment, ₹7,500 crore (about $900 million) of revenue in at least one of the preceding three financial years, a 300-mm (12-inch) wafer facility capable of at least 40,000 wafer starts per month, and production-grade licensed technology. In plain terms, the largest project category now requires roughly 40 cents of every dollar to come from the operator and the rest from the government, on a fab that no Indian startup can build today.

The middle of the stack is where the scheme is most generous. Compound semiconductor, photonics, sensor and MEMS fabs (micro-electromechanical systems, the tiny mechanical-on-chip devices used in phone microphones and airbag sensors) can claim 35% of eligible capex with a ₹500 crore (about $60 million) investment floor and 500 wafer starts per month. Display fabs for OLED, Micro LED, and LCD panels get the same 35% support, subject to technology-specific criteria, per the India Semiconductor Mission scheme page.

The design side is where the genuinely new money lives. Newly launched chips, IP blocks, or system-on-chips with no prior sales can claim 9% of net sales for five years through a chip-deployment incentive. Indian-owned and -controlled design companies can tap seed funding, equity co-investment, or royalty financing through a new commercial chip-design window, while a parallel "strategic" track is open to companies with substantial operations and workforce in India and will award support through a competitive request-for-proposals process, according to the Cabinet press release on Semicon 2.0.

The ₹1.27 lakh crore envelope is about $15 billion, an order of magnitude larger than the per-fab gates would absorb if every eligible project applied. Cutting the per-silicon-fab subsidy from 50% to 40% and adding revenue and technology floors caps how much of the new envelope any one project can absorb, freeing the rest for designers and packagers. IT Secretary S. Krishnan, quoted in the gazette notification, framed the scheme as a move to "the next stage of semiconductor development" aimed at self-reliance and a globally competitive industry.

The 9%-of-net-sales chip-deployment incentive only pays out if the chips sell. The seed and royalty-financing instruments need banks, investors, and procurement officers willing to underwrite small design firms that the Indian venture market has historically avoided. The per-fab cut from 50% to 40% is a real signal to the next wave of mega-fab applicants about how much of any future marquee project India expects the operator to fund.

The first round of requests for proposals under the new design and packaging windows is the next milestone to watch.