HWNEWS
An imec paper shows atomically thin "2D" channels can't out scale silicon at the next node after today's 2 nanometer chips, measured in units called angstroms, a tenth of a nanometer.
The semiconductor industry has been betting that "2D" materials, atomically thin sheets that can stand in for silicon inside a transistor, would let chips keep shrinking past today's 2-nanometer class. A new imec technical paper says the bet is real, but the bottleneck has moved. At the first widely cited angstrom-era node, A2, the wiring that touches the transistor, not the transistor itself, sets the floor on how small a chip can get.
A2 is the next stop on the industry roadmap after today's 2 nm and 3 nm class chips. The "angstrom" label, a unit ten billionths of a meter, signals that conventional silicon geometry is running out of headroom. "2D" here means a transistor channel built from a sheet of material only one or a few atoms thick, rather than a slab of silicon. The hope was that such sheets would keep current flowing where silicon gets too leaky to behave. A team led by imec researchers tested that hope at A2 and found a sharper constraint hiding behind it.
In a paper posted to arXiv this month, the imec group reports a 2D CFET integration flow, a complete device recipe targeting A2, with a contacted poly pitch of 36 nm and a gate length of 10 nm. Contacted poly pitch, or CPP, is the center-to-center spacing of the metal plugs that wire each transistor into a circuit. It is the ruler the industry has used for two decades to track how much logic can be packed into a given area. At 36 nm, the imec 2D flow matches the minimum CPP that silicon CFETs can already hit at A2. The atomically thin channel buys nothing extra on the density axis because contact formation, not channel physics, sets the spacing floor.
The transistor inside the cell can be more exotic; the cell still has to be wired, and the wiring has stopped shrinking. Density gains past this point have to come from contacts and from the parasitic resistance and capacitance that surround them, rather than from the channel material. The finding is a negative one for the "2D replaces silicon" narrative, but it is paired with a positive one: imec's group also lays out a multiscale simulation framework that can test the same question for each future node, with the same ruler.
The framework runs from quantum transport, modeling how electrons actually move through an atomically thin channel, through a compact model, through parasitic extraction on a defined A2 integration flow, and into circuit-level benchmarks for power, performance, and area. The point is not to declare a winner between 2D and silicon. The point is to give the industry a workflow that compares them on the same axis at each new node, instead of leaning on roadmap slides. As the paper puts it, this lets the community decide "node by node" whether the next density step comes from the channel, the contact, or the layout.
The paper is a preprint on arXiv, not a peer-reviewed publication, so the specific 36 nm number and the framework details are imec's own claim until outside groups reproduce them. The imec team also does not extend the analysis beyond A2. A14, A10, and the deeper angstrom-era nodes are out of scope, and the contact wall may not hold at every step. The paper does not make a market or adoption claim; it is a mechanism finding. Read it as one serious entry in a node-by-node evaluation, not as a verdict on whether 2D materials have a future at all.
Reproducing the 36 nm floor under independent simulation is the next concrete task. The imec group, the A2-class foundries, and the equipment vendors who make the contact-formation tools all have the data needed to run the same workflow outside imec. When they do, the industry will have either a shared ruler for the angstrom era or a sharper picture of what is still missing. Either way, the limit is now in the contacts, and the roadmap has to be argued on that ground.