The NanoStack architecture hits 0.7 nanometer gate lengths — the size of the on/off switch in each transistor, measured in nanometers — with IBM claimed 50 percent more performance or 70 percent less power than the company's own 2 nanometer class platform.
IBM just crossed the 1-nanometer line for transistor gate length, but the milestone is not really about making things smaller. The trick was changing direction: stacking transistors vertically rather than continuing to shrink them sideways. The new architecture, called NanoStack, was announced June 25, 2026 and reported in detail by Live Science, with the technical basis laid out in an IBM Research paper presented at the 2025 Symposium on VLSI Technology and Circuits.
The 0.7-nanometer figure refers to the gate length, the size of the electrical switch that turns each transistor on and off. IBM built it using vertically stacked, alternating n-type and p-type nanosheets, a geometry the company describes as a "stacked forksheet" arrangement. Today's 2-nanometer-class chips already use gate-all-around nanosheets, but the n-type and p-type devices sit side by side on the silicon. NanoStack staggers them on different vertical levels, so the same footprint can pack more current-carrying layers without further lateral squeeze. IBM Research explains the rationale: the industry had run out of room to keep cutting dimensions sideways because doing so raises current leakage and heat density, the two walls that have threatened to flatten Moore's Law for a decade.
IBM's performance claims follow directly from that geometric change. The company says a NanoStack-based test vehicle shows roughly 50 percent more performance or 70 percent less power draw compared with its own 2-nanometer-class reference platform at comparable area, with room to demonstrate up to 100 billion transistors in a fingernail-sized die. Those numbers come from IBM's own benchmark methodology, not independent testing, and they apply to a research device rather than a shipping chip. They are also a single-vendor, same-platform comparison, not a cross-foundry shootout. The honest read: vertical stacking preserves a real scaling path, and IBM has the only working hardware that demonstrates it at sub-nanometer gate length today.
The framing matters because "nanometer" in chip marketing no longer tracks a single physical dimension. A "2nm" process name is a generation label, not a measurement of any specific transistor feature. The 0.7nm number in IBM's announcement is a real dimension, the electrical gate length on the test device. Confusing the two is the easiest way to misread the announcement, and the Live Science report explicitly flags that risk.
The competitive picture gives the timing some weight. TSMC has publicly targeted sub-1nm production by 2029, Samsung's 2nm gate-all-around work is at an earlier yield stage, and mainstream EUV lithography sits at the boundary of A14 and 2nm-class manufacturing. IBM's announcement does not collapse that timeline. It is a research demonstration from a long-running Albany NanoTech collaboration with Samsung and others, and the company positions it as a path, not a product, with its own roadmap pointing toward 0.1nm-class devices further out.
What is genuinely new is the architectural answer to a known problem. The CMOS heat and gate-leakage constraints that block purely lateral scaling at this geometry do not vanish just because the geometry changed. Charge trapping, leakage currents, and thermal density remain real manufacturing challenges, and high-volume manufacturing of stacked nanosheets will require new process steps. But NanoStack shows the industry has a tool that is not just another round of side-by-side shrinkage. The next milestones to watch are when IBM or a partner translates the test vehicle into a yieldable process module, and whether TSMC's own 2029 sub-1nm target uses a comparable vertical approach or bets on a different trick entirely.