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IBM stacks transistors in 3D to fit 100 billion on a fingernail-sized chip
The 'nanostack' architecture reframes the post Moore scaling question: instead of shrinking transistors laterally, IBM stacks and staggers them vertically.
The 'nanostack' architecture reframes the post Moore scaling question: instead of shrinking transistors laterally, IBM stacks and staggers them vertically.
IBM didn't shrink a transistor. It stacked one.
That single move reframes the question that has haunted chipmaking since Gordon Moore's 1965 forecast that transistor counts would roughly double every two years. For decades the answer was always the same: make each transistor smaller and pack more of them side by side. On June 25, 2026, IBM unveiled what it calls the world's first sub-1-nanometer chipmaking process, and the substance of the announcement is not that the transistors got smaller. It is that they got stacked.
The demonstration die is roughly the size of a fingernail and holds around 100 billion transistors, each with features of about 0.7 nanometers, smaller than a strand of DNA, which measures about 2.5 nanometers across. IBM says the architecture delivers nearly double the transistor density of its 2021 2-nanometer chip and up to 70 percent greater energy efficiency at equivalent performance.
The trick is what IBM calls NanoStack: instead of laying transistors out flat on the silicon and shrinking each one laterally, the new design stacks them in three dimensions and staggers them so current can still flow. Think of it as the difference between cramming more books onto a single shelf and adding another shelf above it. Lateral scaling was running into a wall set by the physics of the gate, the switch that turns each transistor on and off. Building upward routes around that wall rather than breaking through it.
IBM's framing matters here. In its technical publication on the NanoStack architecture, the company ties the work to the so-called "CMOS 7A node and beyond," a named process generation rather than a single finished chip. The announcement is a manufacturing milestone, not a product you can buy, and the company estimates production is roughly five years away. [[Ars Technica]](https://arstechnica.com/gadgets/2026/06/ibm-claims-worlds-first-sub-1-nanometer-chip-technology/), EE Times, and CRN all covered the announcement on the same day, but none produced third-party benchmarks.
That leaves the headline numbers sitting where IBM put them: as company claims on a research demonstration. Jay Gambetta, director of IBM Research, said in the announcement that the work is "reinventing how chips are built" rather than continuing to shrink them. The architectural shift is the durable part of the story. Whether the precise figures, roughly 2x density and 70 percent efficiency, hold up under independent test is the part to watch.
For a chip industry that has spent a decade asking what comes after Moore's Law, IBM's answer is not a smaller switch. It is a taller room. The next test is whether the rest of the industry, from foundries like TSMC and Samsung to design houses and the AI compute buyers waiting on the other side, agree this is a path worth following, and how quickly.