The 'memory wall' is the bottleneck where on chip memory can't keep up with processor speed, now a bigger limit on AI chips than raw transistor counts. IBM's 3D stacked architecture attacks it, but production is still five years out and the foundry partner is undecided.
The bottleneck that decides whether an AI chip is fast is no longer how many transistors it has. It's how fast those transistors can be fed with data. IBM's latest research bet makes that shift explicit: a new transistor architecture called nanostack, the company says, is built to attack the so-called memory wall by stacking transistors in three dimensions so more fast on-chip memory sits closer to the processor.
At a research event reported by EE Times, IBM framed the design as the first chip-manufacturing technology to break the 1-nanometer threshold, with a 0.7-nm marketing node that packs nearly 100 billion transistors onto a single die. The figure roughly doubles the density of IBM's first 2-nm nanosheet device from 2021 and signals the company's intent to push the so-called "nanosheet" gate-all-around architecture, the same family now entering 3-nm and 2-nm production at TSMC, Samsung, and Intel, into another decade of scaling.
The memory wall is the widening gap between compute speed and the speed at which on-chip memory, typically SRAM, can deliver data to that compute. SRAM is the fastest memory that lives on the processor itself, and cramming more of it into the same physical area is one of the harder problems in chip design. As transistor counts have multiplied, processors have spent more of their cycles waiting for data than doing arithmetic.
IBM's answer is vertical. The company's research publication at VLSI Technology and Circuits 2025 describes nanostack as a 3D stacked architecture: two transistors built on two nanosheets, one stacked above the other, each sheet about 5 nm tall, roughly 15 silicon atoms, with a 9 nm gap between them. Stacking turns a flat transistor layout into a tower, letting designers double density without shrinking the horizontal pitch. IBM research director Jay Gambetta said the company demonstrated roughly a 40% improvement in SRAM scaling compared with 2 nm, framed as a step change in a metric that is becoming more important than raw transistor counts.
The catch is that none of this is on a production line. EE Times reports that IBM vice president of global semiconductor R&D Huiming Bu described nanostack as a device platform intended to keep scaling viable for another decade, with production readiness targeted within five years. That horizon is IBM's own goal, not an industry consensus schedule, and it sits well beyond the 2-nm nanosheet production that IBM and Japanese foundry partner Rapidus are already working toward for next year. The question of which foundry will eventually manufacture nanostack, whether Rapidus, Samsung, or another partner, remains unresolved, according to Gambetta, and IBM has not committed to a transfer.
This is also a research result, not a manufacturing yield. IBM's own press materials and ZDNets coverage of the VLSI 2025 publication frame the 40% SRAM improvement as a demonstration figure, validated in a research setting rather than in a high-volume fab. The "sub-1-nm" and "0.7-nm" labels are also marketing-node names, not literal physical gate lengths or pitches, so comparisons to historical process nodes should be read as IBM's framing, not as a measurement in the same units as older chips.
The architecture is not the only signal that the industry has accepted the memory-wall framing. EE Times cites Tenstorrent and its Galaxy Blackhole processor, designed by Jim Keller's team, as a chip company actively pushing more SRAM onto the die to scale AI workloads, a third-party example that the architectural shift is happening at the product level, not just in research labs. And IBM and equipment maker Lam Research announced a collaboration in March 2026 to advance sub-1-nm logic scaling, suggesting the design is being lined up against the deposition and etch tooling that any future fab would need.
What to watch next: the foundry partner decision, which turns nanostack from a research result into a real production path; the outcome of the Lam Research collaboration, which will determine whether the equipment side of the supply chain can actually pattern a 0.7-nm-class architecture; and the first 2-nm nanosheet parts from Rapidus, which would tell the industry whether the prior generation is delivering on its own scaling promises before the next stack arrives.