IBM's research process is branded at 7 angstroms (a tenth of a nanometer, about the diameter of a small atom), layers transistor channels vertically, and projects up to 50% more performance and 70% better energy efficiency than its own 2nm node, though no production timeline has…
IBM has shown a research chip process that pushes below the 1-nanometer line not by breaking physics, but by stacking transistor channels vertically inside the same reticle-area constraint that has bounded Moore's Law for two decades. The reveal, branded at 7 angstroms, extends the gate-all-around (GAA) nanosheet architecture IBM used at its prior 2nm node into a multichannel nanosheet-on-nanosheet "NanoStack" configuration with vertical isolation between the stacked transistor channels, as documented in the company's June 25 announcement.
IBM claims the architecture delivers up to 50% more performance and 70% better energy efficiency than its own 2nm node, alongside a 4-track staggered cell design that projects roughly 50% area improvement, meaning each logic cell fits more densely into the same die footprint. These figures come from the company's own modeling against its prior node, not third-party benchmarks on shipping silicon, and the announcement is a research and roadmap reveal rather than a foundry production commitment.
To translate the unit: an angstrom is one ten-billionth of a meter, a tenth of a nanometer, and roughly the diameter of a small atom. So 7 angstroms is 0.7 nanometers, well under the 1-nanometer threshold the press release headlines. Like most process node names, though, "7 angstrom" is a label, not a measured physical gate length. The technical record lives in IBM's NanoStack Transistor Architecture publication and the company's research blog post on the sub-1nm node, which document SRAM test-vehicle work for the 7A generation.
Why this matters now: AI training and inference are power- and density-bound. Any geometry win that compounds performance per watt inside the reticle, the maximum die size a lithography tool can print in one shot, moves the AI compute cost curve. IBM explicitly targets high-end AI data centers with this technology. The reticle limit has not gone away, but chiplet designs (where smaller dies are integrated inside a single package), HBM (high-bandwidth memory) stacks, and now transistor-level 3D stacking let chipmakers route around it instead of waiting for a single die to grow.
Several details from the wire coverage deserve careful framing. The "100 billion transistors" figure in some headlines aggregates device counts across the stacked NanoStack structure; it is not a single-die transistor count. The R&D sits inside the Albany NanoTech Complex public-private partnership, and IBM does not own a leading-edge fab, so the path from research paper to manufactured product runs through a foundry partner. Secondary outlets like Tom's Hardware, Semiconductor Digest, and Electronic Design largely restate the IBM press release. Futurum's analyst note is the closest thing to independent interpretation, and it correctly argues that the NanoStack architecture, not the 0.7nm label, is the real story.
What to watch: which foundry, if any, picks up the vertical-stacking concept, and on what timeline. The 50% performance and 70% efficiency numbers are IBM's own projections against its prior node, so the harder test is whether third-party silicon replicates the gains once the architecture leaves IBM's research cleanroom.