IBM's sub nanometer NanoStack transistor design claims 40% more on chip SRAM (the fast, embedded cache that lives on each processor) and frames it as faster than HBM (the stacked DRAM that sits beside accelerators).
The AI chip story of the last few years has been told as a bandwidth story: stack more HBM memory channels, widen the bus, throw more silicon at the off-chip bottleneck. This week IBM made a different bet.
The company's new NanoStack transistor architecture, built at 7 ångströms (a unit of length roughly equal to one atomic radius, or about 0.1 nanometers), is engineered less around raw transistor density and more around one specific resource: SRAM cache, the small, fast memory that lives directly on the processor and feeds it instructions faster than any external memory can. IBM says its staggered nanosheet design enables roughly 40% better SRAM scaling, plus either up to 50% performance gain or up to 70% power efficiency. The architecture is documented in a NanoStack research paper and a VLSI 2026 paper on staggered-channel bitcells.
The subtext is strategic. IBM explicitly positions NanoStack SRAM as faster and lower-latency than HBM (high-bandwidth memory, the stacked DRAM chips that sit beside AI accelerators), a pointed contrast in a year where every AI accelerator vendor has been racing to widen HBM capacity and push HBM4 and beyond. IBM's framing: if the on-chip cache can carry more of a model's working set, less data needs to round-trip to HBM at all, and the bandwidth wars become less binding. Memory-side research is heading the same direction: high-bandwidth flash (HBF) is emerging as a capacity-oriented complement layered on HBM-style channels, as Hyper Accel explains, which suggests the industry sees the off-chip hierarchy as the binding constraint worth working around or expanding.
The production horizon keeps this in the lab for years. IBM is targeting mass production around 2031, per the company's announcement. The performance, efficiency, and SRAM-scaling figures are all vendor-stated, drawn from IBM's press release and the NanoStack paper rather than independent silicon benchmark data. Until production chips exist, the bet is architectural, not empirical.
IBM is not alone in the sub-nanometer hunt. Researchers at the University of Tokyo reported one-nanometer semiconducting molybdenum disulfide (MoS2) nanotubes as a candidate channel material for ultra-scaled gate-all-around transistors, a different path toward more transistors in less space, summarized in this week's Chip Industry Week In Review roundup. That work is research-stage with no production timeline, a parallel proof of concept rather than a rival to IBM's staggered nanosheets.
The biggest business move of the week was a planned acquisition, not a chip. Onsemi, a supplier of power-management and sensing chips for industrial and automotive customers, announced an agreement to acquire Synaptics for roughly $7 billion, with a target close in mid-2027. Synaptics makes touch controllers, display drivers, biometric sensors, wireless connectivity, and edge-AI compute silicon. Onsemi CEO Hassane El-Khoury framed the combination as positioning the merged company for "physical AI": sensors and compute bundled at the edge, in factories, vehicles, and robots, rather than in distant data centers. The deal is announced, not closed; regulatory clearance and integration risk remain on the table.
The rest of the week rounded out a familiar consolidation pattern. AI memory and inference infrastructure kept tightening: Qualcomm and Modular announced an AI software deal, OpenAI and Broadcom were reported to be co-developing a custom LLM inference chip, Micron and Anthropic disclosed a memory-and-storage partnership, Groq raised $650 million and licensed its LPU technology to Nvidia, and Advantest partnered with OpenLight on photonics test. Applied Materials rolled out new epitaxy, CMP, deposition, and e-beam tools. Chinese OSAT JCET was reported to be planning a roughly $1.15 billion advanced-packaging site in Shanghai. Swedish startup AlixLabs unveiled an ALE pitch-splitting tool. GlobalFoundries pushed 9SW RF-SOI with wafer-to-wafer bonding. A CHIPS Act award of roughly $250 million and a new trade-secret theft case added the policy and litigation backdrop.
The frame worth holding is not which company wins on transistor size but which resource unlocks the next AI workload. IBM's bet is that on-chip cache density does. HBM vendors are betting that bandwidth and capacity do. Both bets will coexist in production for years; the question is which one binds first as model sizes keep scaling.
What to watch: independent benchmark data on NanoStack SRAM density and latency once IBM shares silicon measurements or an external fab replicates the bitcell; the regulatory and closing path of the Onsemi-Synaptics deal toward mid-2027; and whether any AI accelerator vendor publicly reorients on-chip cache scaling from a secondary to a primary design target.