Hitachi and Intel will try to build a quantum computer on a real chip factory line

Hitachi is going to try to make quantum hardware the way Intel makes regular chips: under the same Process Design Kit and 18A process rules that govern every other transistor on a modern chip. The bet is that a useful quantum computer is now a yield-engineering problem, not a physics problem, and Japan's New Energy and Industrial Technology Development Organization (NEDO) just put a March 2029 deadline on whether the bet works.

NEDO selected Hitachi to lead a three-year R&D initiative titled "Accelerating the Development and Demonstration of Next-Generation Quantum Computers to Solve Social Challenges." The partners are Intel K.K., Intel's Japanese subsidiary, and the Global Research and Development Center for Business by Quantum-AI Technology (G-QuAT), a unit of Japan's National Institute of Advanced Industrial Science and Technology (AIST). The work targets silicon spin qubits, quantum bits encoded in the spin of a single electron trapped in silicon, which researchers have long hoped can ride the same manufacturing infrastructure that produces conventional processors.

The program is split across four tracks, each tied to a specific manufacturing constraint. Hitachi will design 100+ qubit processor chips using Intel's specialized Process Design Kit for quantum devices on Intel's 18A process, the same foundry rulebook that governs a phone's main processor. Track two is low-power cryogenic packaging and control circuits: the wiring and electronics that have to sit at temperatures near absolute zero. Track three targets 3D high-density integration with an explicit goal of scaling to 1,000+ qubit arrays. Track four is cloud platform integration at G-QuAT, where outside researchers and corporate partners will eventually log in to run real workloads.

The Process Design Kit is the lever. PDKs are the rulebooks chip designers follow to hit a foundry's tolerance targets, and Hitachi is betting that the kit used for advanced logic chips can constrain device-to-device variation in qubits tightly enough for a useful machine. Silicon spin qubits can in principle use existing fabs and EUV lithography, but scaling to the million-qubit level required for fault-tolerant quantum computing, the term for machines reliable enough to run real-world calculations, has been blocked by exactly the variability and cryogenic-wiring problems this program exists to solve, according to the program announcement.

The milestones give the bet a clock. In FY2027, AIST's G-QuAT center is scheduled to open an experimental cloud service so external researchers and companies can run workloads on the new hardware for the first time. By the program's end in March 2029, Hitachi and its partners want to demonstrate that 18A-fabricated spin-qubit chips can move from 100+ qubit prototypes toward the 1,000+ qubit arrays track three targets. Specific FY2028 commercial execution milestones appear in Hitachi's roadmap but were not visible in the available source excerpt.

The honest test is whether foundry discipline, not new physics, becomes the gating constraint. If FY2027 cloud users can run useful circuits on 18A-fabricated qubits, the manufacturing playbook starts to look like the answer. If variability and cryogenic wiring still dominate, the program ends as another data point in a longer roadmap.