Google is reported to move its next AI chip's packaging from TSMC to Intel — the layer that has throttled AI deliveries for two years

The supply chain that decides how many AI chips the world actually gets has moved — from the silicon itself to the wiring layer that joins multiple chiplets into a single working processor. That wiring layer is called advanced packaging, and it has been the binding constraint on AI chip deliveries — not transistor scaling — for roughly two years, based on a synthesis of the available reporting.

The wire debate has been calling this a foundry race. It is not. The chokepoint sits downstream, where multiple small silicon tiles get stitched into one package large enough to do AI work. The previous supplier does that stitching with a silicon interposer carrying embedded bridges; the new entrant does it with silicon bridges embedded directly in the package substrate, routing power vertically through the stack. Functionally interchangeable, structurally different — and now, for the first time at hyperscaler scale, a credible second source.

Tom's Hardware, citing SemiAnalysis, reports Google as the hyperscaler making the move — choosing Intel's EMIB-T for its ninth-generation TPU codenamed Humufish after a run on TSMC's CoWoS that began with the third-generation TPU. Ming-Chi Kuo independently corroborates the switch. For any future AI chip announcement, the question stops being who made the silicon. It is who did the packaging.