HWBRIEF
DRAM is the working memory in phones, laptops, and AI servers; the simulator now covers three cell designs, including 3 D stacked variants for chips that compute inside memory.
A free, peer-reviewed DRAM simulator from Georgia Tech just got a sequel, and it targets the part of AI hardware that rarely makes the launch slides: the data-shuffling tax between processors and memory.
The Open DRAM Model Part II, published in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (vol. 12, pp. 144–152, 2026; DOI 10.1109/JXCDC.2026.3704508), extends the original release to scaled 4F² VCT cells and monolithically stacked 3-D DRAM, alongside the conventional 6F² BCAT baseline. Companion code lives on GitHub at MATRIX-PDK/OpenDRAMmodelV1, with the maintainer Shimeng Yu group's downloads page.
The release is a research enabler, not a chip. No foundry or EDA partner is attached, and there is no benchmark dethroning an incumbent. What it offers is a SPICE-level view of bitline sense amplifiers, triple-row activation, and majority-logic operations in realistic DRAM cells, the kind of public infrastructure that lets academic and small-team groups test processing-in-memory designs before committing to a fab run.
The SemiEngineering write-up frames the broader industry context. What remains unknown is whether any major memory maker or AI accelerator team will adopt or extend the model.