HWNEWS
AI racks are moving to 800 volts, and the bottleneck is the final foot down to the chip, where today's two stage converters waste about 14% of the power as heat.
NVIDIA used the OCP (Open Compute Project) Global Summit to outline a new 800-volt DC blueprint for AI data centers, replacing multiple AC-to-DC conversion stages inside AI factories with a single high-voltage direct-current bus. The bottleneck that does not show up in the rack-level diagram is the final foot: 48 volts stepped down to roughly 1 volt at the chip, where the mainstream two-stage design loses about 14% of the energy as heat.
The 800-volt DC bus is the part the white paper actually solves. Higher voltages mean lower currents for the same delivered power, which cuts resistive losses in the copper busbars running from the substation to the rack. Long-distance DC transmission at 800 volts or higher is a solved problem at the grid scale; the white paper's move is to bring that approach inside the data center, all the way to the rack. What the rack-level diagram does not show is what happens next.
On that final stretch, today's mainstream design is a two-stage chain. A first-stage converter drops 48 volts to a 12-volt intermediate bus, peaking around 96% efficiency. A second-stage multi-phase buck converter drops 12 volts to the chip's core voltage, peaking around 92%. Multiplied together, the chain peaks at roughly 88% before system-level losses, and once distribution losses, parasitic impedance, and other real-world factors are counted, the two-stage path delivers only about 86% end-to-end efficiency, according to an EE Times analysis of the architecture.
AI processors are now in the kilowatt class, with core voltages near 0.8 to 1.1 volts and load currents in the kiloampere range that swing on microsecond timescales. A point-of-load (PoL) DC/DC converter sitting next to the processor handles the final step, and the same EE Times analysis frames that last segment as where data-center efficiency, density, and heat actually get decided.
EE Times's analysis points to a single-stage alternative, a 48-volt-to-ultra-low-voltage converter called the HP1800, that would skip the intermediate 12-volt bus. The piece positions the design against the two-stage baseline, and the part number is named, but the manufacturer is not identified in the publicly available excerpt, and Type0 could not independently anchor the HP1800's specific efficiency claims or commercial status before publication.
NVIDIA's white paper, also surfaced at the OCP Global Summit, claims the wider 800-volt DC architecture delivers up to 26% space savings inside AI factories compared with traditional multi-stage conversion. That figure, attributed to NVIDIA in the EE Times coverage, is a rack-level claim, not a chip-level one, and refers to the saved power-conversion hardware along the bus from the substation to the rack, not to the final 48-volt-to-chip step.
The two-stage design persists for a reason. EE Times describes it as the industry mainstream precisely because of supply-chain maturity, EMI (electromagnetic interference) control, and component-availability reasons that any single-stage alternative would have to match. A shift from two-stage to single-stage would require more than an efficiency win; it would require an entire ecosystem of magnetics, controllers, and safety components to mature alongside the new topology.
Watch item: the next move to watch is the final foot to the chip, not the rack bus. The roughly one-volt output that AI accelerators actually use is where single-stage converters have to prove they can move from a product curiosity to a rack-ready architecture, and the next round of vendor silicon, white-paper revisions, and OCP reference designs will show whether they do.