HWBRIEF
DiffPower converts a chip's gate level wiring (the netlist physical design tools read) into portable bytecode and uses gradient based optimization, so power can be tuned alongside timing and area during design.
Duke and Synopsys researchers have posted a preprint describing DiffPower, a GPU-accelerated tool that estimates how much power a chip will draw during real operation. On the largest design the team evaluated, the tool ran up to 1,002 times faster than a single-threaded CPU reference, and the GPU advantage widened as designs scaled.
DiffPower is also differentiable, meaning it can compute gradients. That lets an optimization loop search intelligently instead of brute-forcing. To get there, the team translates a chip's netlist, the gate-level connectivity description that physical-design tools read, into a process-portable bytecode that works across different foundry kits, then runs an analytical model and parallel simulation in tandem.
The reported numbers are large but bounded. Across ten industrial and benchmark designs, the hybrid approach reached a median toggle-rate correlation of r=0.96 with the CPU reference. Power gradients came out up to 904 times faster than CPU finite-difference methods, and the team used those gradients to shrink cells for lower power (up to 2.98x more improvement than local-power heuristics at 117K cells) and to generate worst-case stress patterns (up to 2.13x higher transition-weighted power than a brute-force search that traditionally takes hours).
The catch: arXiv:2608.03778 is a preprint, not peer-reviewed work, and the authors describe an academic and industry collaboration rather than a Synopsys product roadmap.