Diraq linked silicon spin qubits—quantum bits carved from single electrons trapped in silicon transistors—to an NVIDIA GH200 Grace Hopper superchip via NVQLink, a low latency interconnect, hitting a ~3.3 microsecond round trip that lets the GPU read each qubit, decide what to do…
When Diraq wired its silicon spin qubits to an NVIDIA GH200 Grace Hopper superchip via NVQLink, the GPU didn't become a quantum computer. It became the system. The qubit, the part of the machine the field has spent two decades obsessing over, just became its slowest, most expensive peripheral.
The Australian hardware startup announced the integration this month, reporting a round-trip latency of roughly 3.3 microseconds between its qubits and the GH200. That number matters less for raw speed than for what it enables: a control loop tight enough that the classical processor can read the quantum chip's state, decide what to do next, and write a new instruction back, all before the qubit's fragile quantum information decays—compressing roughly a year of human calibration work into days.
For a reader who has never set foot in a quantum lab, the doorway is this. A silicon spin qubit is a quantum bit carved into ordinary semiconductor material, exploiting the magnetic orientation of a single electron trapped in a transistor-like structure. The trick is that Diraq can build these qubits the way Intel builds processors, on silicon wafers in fabrication plants, rather than hand-assembling exotic hardware the way rival modalities such as superconducting circuits or trapped ions require. The hard part isn't making them. It's running them.
Every working qubit needs a surrounding stack of voltages, microwave pulses, and measurement cycles tuned precisely enough that the qubit behaves quantum-mechanically rather than collapsing into noise. Most of that work is calibration: sweeping voltages, mapping charge stability (the conditions under which an electron sits still long enough to act as a qubit), and fitting parameters until a specific qubit cooperates. Today, much of that work is done by expert physicists at a bench, and the source reports it can absorb the equivalent of roughly one physicist-year per machine.
Diraq says it has compressed that workload to model training that completes in days, by handing the charge stability map analysis to NVIDIA's Ising models: open vision and language models the company has fine-tuned for the job, running on the GH200. The Ising model reads the map the way a vision model reads an X-ray, finds the operating points where a qubit is stable, and writes the calibration parameters back. The GH200 is doing the calibrator's job.
NVQLink is the piece that makes this practical. It is NVIDIA's low-latency interconnect, designed specifically to bind a classical accelerator like the GH200 to quantum control hardware so the two can pass data fast enough to close the loop in real time. Without it, you can still run quantum algorithms on a GPU, but you cannot run a quantum experiment that adapts to its own results mid-flight. With it, the GH200 effectively sits inside the experiment rather than next to it.
The interesting consequence is what disappears from the bottleneck. For most of the quantum hardware era, the binding constraint on scale was qubit count, then qubit fidelity, then error correction. Diraq's results suggest a fourth constraint is moving up the stack: whoever controls the classical control plane controls the pace of the field. The qubit needs the GH200 more than the GH200 needs the qubit.
That framing comes with limits worth naming. The 3.3 microseconds is a control-loop figure, not a speed-of-computation claim. The automated calibration covers charge stability tuning but not the full stack of error correction and crosstalk management, which still sits with human physicists. "Utility-scale" in the announcement is aspirational framing for an engineering target, not a measured milestone: Diraq's published qubit counts remain far below the millions-per-chip figure silicon manufacturing ultimately promises. And NVIDIA has not endorsed Diraq's roadmap beyond the integration itself. The source for all of these numbers is a single trade-publication writeup, so independent confirmation is the open question.
What has changed is the shape of the dependency. When calibration, error decoding, and adaptive experiment design all run on the same GPU that orchestrates AI training on the data-center side, silicon-spin quantum computing stops being a craft and starts being an extension of the AI factory floor. The control plane becomes the platform, and the qubit becomes its I/O device. Rent potential, not qubit count, is now the variable worth watching.
What to watch next: whether peer-reviewed or preprint results from Diraq confirm the 3.3 microsecond figure outside the company's own writeup; whether NVIDIA's CUDA-Q programming layer becomes the default way silicon-spin experiments are written; and whether the calibration automation generalizes beyond charge stability maps to the rest of the tuning stack. The first time a non-Diraq team runs a multi-qubit adaptive experiment on a GH200-class controller, the control plane will have stopped being optional.