Eight silicon spin qubits on imec's 300 mm CMOS production line held millisecond coherence in a new Nature Communications paper, reframing quantum scaling as a semiconductor manufacturing problem.
Diraq and imec have run an eight-qubit silicon spin qubit array on a commercial 300 mm CMOS production line and watched it hold millisecond-scale coherence. The result, published this week in Nature Communications, reframes the quantum hardware race: the next limit on scaling silicon-based quantum computers is no longer the physics of the qubit. It is the discipline of the fab that builds it.
Spin qubits are single-electron spins trapped inside tiny patches of silicon, controlled by the same kind of voltages a classical transistor uses. Their appeal, in a field crowded with trapped ions, superconducting circuits, and neutral atoms, is manufacturing: in principle, the chips can be made on the same foundries that stamp out billions of conventional processors. The Diraq/imec paper is the cleanest demonstration yet that the "in principle" survives contact with a real high-volume line.
The device is an 8-dot linear chain organized as four double quantum dot (DQD) unit cells, fabricated by imec's 300 mm SiMOS process on a substrate of isotopically purified silicon-28, the same isotope engineering used to suppress nuclear-spin noise that would otherwise decohere the electron's quantum state. According to the arXiv preprint of the Nature Communications paper, all eight qubits tune cleanly and behave as four independent two-qubit modules. The array shows Ramsey dephasing times T2* up to 41(2) microseconds and Hahn-echo coherence times up to 1.31(4) milliseconds. The authors treat the numbers as a system-level benchmark for the foundry-built device rather than a record claim against any other platform.
Beyond the qubit count, two parts of the design carry the result. The team replaced per-qubit charge sensors with a cascaded protocol that reads the central four qubits in just two steps, an architectural compression that turns a single chip into something a fab can actually route. They also demonstrated a two-qubit gate between adjacent qubits with low phase noise, showing that the foundry-built material supports the entangling operations a multi-qubit algorithm requires, not just the single-qubit control earlier two-qubit demos had established.
The signal lives in manufacturing discipline. Imec's 300 mm SiMOS line is the same kind of production tool that builds advanced CMOS logic for hyperscalers and image sensors for consumer cameras. Until now, every published multi-qubit spin device was built either in a university cleanroom or on a smaller dedicated line, with qubit-grade uniformity maintained by hand rather than by process control. Quantum Computing Report's summary of the announcement frames the milestone in manufacturing terms: the question is no longer whether the same fabs that build classical chips can also build quantum ones, but how far the foundry roadmap can carry both at once.
Diraq, an Australian spin-out of Andrew Dzurak's UNSW group, has built its roadmap around the bet that silicon spin is the only qubit platform whose scaling story overlaps with the global semiconductor capital cycle. The bet pays off when device coherence is set by fab uniformity rather than lab heroics. The Nature Communications result is the first time that bet has cleared peer review at the eight-qubit scale, on a 300 mm commercial line, with coherence and gate control demonstrated together rather than separately.
The authors flag the caveat themselves: the coherence numbers describe one device, in one fabrication run, on isotopically enriched silicon that is itself a bottleneck for any commercial roadmap. Volume manufacturing of pure silicon-28 is its own engineering problem, and the authors do not claim the array sets a record against other platforms, only that a foundry-built device can preserve the coherence and gate control previous work had only shown on smaller lines. The falsifiable version of the manufacturing-paradigm story is whether the next wafer run, on the next process node, reproduces these numbers without per-device tuning.
What to watch next: imec's downstream 300 mm spin-qubit roadmap, and whether the cascaded charge-sensing architecture survives a 16- or 32-dot extension. Diraq has said it will target utility-scale silicon systems within the decade, and the relevant question for the rest of the industry is whether that target is now a physics problem they have to solve, because the rest of the path is a fabrication problem they can buy.