Optical links today are separate pluggable modules bolted onto circuit boards; the next leap puts them inside the same chip package as the silicon, and MIT researchers are one of several academic groups trying to make it work in ordinary chip factories.
The world is building data centers faster than the grid can sustain them. By one widely cited projection, those facilities could consume close to 10% of global electricity by 2030, and the standard way of moving data off a chip, pluggable optical modules bolted onto circuit boards, cannot scale to AI's bandwidth demands without blowing through that energy budget. The exit ramp a growing research community is betting on is co-packaged optics: putting the light-moving photonic components into the same chip package as the silicon they feed, so data crosses shorter distances using less energy per bit.
That shift sounds simple. It is not. Photonic devices are typically built on different materials and processes than standard CMOS electronics, and getting light to flow cleanly between two chips stacked inside the same package, or between a chip and an optical fiber, is a coupling problem. The MIT News release, summarizing work led by Anu Agarwal and the FUTUR-IC program, pegs a target of more than 1 petabit per second per package, up from hundreds of terabits per second today. That goal was articulated by Agarwal in an April 2025 MIT Industrial Liaison Program webinar titled "Shaping the Future of Semiconductors: Power, Performance, and Possibility".
The headline device emerging from MIT is an evanescent coupler designed to make electronic-photonic co-packaging easier, covered in August 2025 by MIT's Materials Research Laboratory and trade publication Laser Focus World. A separate, adjacent result, a GRIN (graded-index) coupler for chip-to-chip and fiber-to-chip photonic packaging, appeared as a preprint in February 2025, with metadata also surfacing in the Journal of Physics: Photonics. The two devices address different geometries, but both target the same manufacturing reality: the couplers are designed to be built with existing equipment in traditional electronics foundries and packaging houses. That is the cost-and-scale pitch. If the photonic glue has to be made in a specialty fab, co-packaged optics will never reach the volumes data centers need.
Independent tracking confirms the device class is more than a one-lab curiosity. A January 2026 review in Nature Light: Science & Applications surveyed advances in waveguide-to-waveguide couplers for 3D integrated photonic packaging, the same problem MIT is working on, and framed it as an active, externally-watched research front. Earlier academic results, including a free-form micro-optics coupler published in Laser & Photonics Reviews in 2023, give the MIT work a prior-art baseline to measure against.
The structural case for this is straightforward. MIT News cites roughly 500 megatons of CO2-equivalent lifetime emissions from microchips in 2021, more than 50 megatons of e-waste per year, and that data-center electricity curve heading toward 10% of world demand by 2030. Photonics helps the bandwidth-energy curve per bit moved, but it does not by itself fix the underlying electronics footprint. The FUTUR-IC program, established in 2022 and partly funded through the NSF Convergence Accelerator, is the institutional vehicle for that argument. Agarwal's pitch to industry: today's data-center architecture cannot scale to projected AI bandwidth without breaking its energy budget.
What to watch next: whether evanescent and GRIN-style couplers can be built at wafer scale in mainstream foundries without bespoke process steps; whether the >1 petabit per second target moves from program aspiration to measured system result; and whether independent industry deployment validates the energy-per-bit gains trade press has so far only sketched. The research is real and externally tracked. The supply chain is not yet built.