A $1.57 million NSF sub grant through the National Quantum Virtual Laboratory will let the Yale led ERASE (Erasure Qubits and Dynamic Circuits for Quantum Advantage) team wire 'erasure qubit' hardware — chips that flag their own dominant decay events, so error correction…
Standard superconducting qubits fail in ways that look identical to correct outputs. A decay event erases the quantum information but does not announce itself, so error-correction software has to do expensive detective work to find out where, when, and how the answer went wrong. That tax is the main reason fault-tolerant quantum computing still feels far away.
A $1.566 million NSF sub-grant to D-Wave Quantum Inc. (NYSE: QBTS) is now funding a different approach: hardware that flags its own dominant decay events natively, so the decoder does not have to guess. The award, made through the National Quantum Virtual Laboratory (NQVL) program, moves the Yale-led ERASE consortium (Erasure Qubits and Dynamic Circuits for Quantum Advantage) from a design competition into Phase II implementation, as reported by Quantum Computing Report. The full ERASE envelope is roughly $4 million over two years, and D-Wave's slice is the industrial partner award.
The architecture at the center of the project is dual-rail erasure encoding. In a standard superconducting qubit, energy decay, the most common error mode, is silent. In a dual-rail circuit, the qubit's information is split across two modes or two physical qubits, and the dominant decay path telegraphs itself: a photon loss, a leakage event, or an atom loss collapses the wavefunction in a known direction. The hardware, in effect, raises its hand before error correction starts. The practical consequence, if the encoding works at scale, is a much lighter error-correction load: lower gate counts, simpler decoders, and a faster path to fault-tolerant operation than the deep surface-code overhead most superconducting roadmaps assume.
ERASE researchers will not be touching the hardware directly. Access is delivered through Quantum Circuits, LLC, a New Haven-based gate-model subsidiary that D-Wave acquired to anchor its superconducting program. Quantum Circuits began life as a Yale spin-out working on superconducting gate-model hardware. The New Haven wiring of the project (Yale researchers, Yale-spinout hardware, Yale-adjacent federal funding, executed at a D-Wave-owned New Haven site) is part of why this is more than a routine sub-contract.
The award is also a federal validation for D-Wave's strategic pivot. D-Wave built its name on quantum annealing, a heuristic optimization approach that is not the same thing as a fault-tolerant gate-model machine. The Quantum Circuits acquisition was the company's move into gate-model hardware, and an NSF-backed consortia test on that hardware gives the company something the public markets have been waiting for: a credible, federally referenced, university-vetted lane into the gate-model race. The company's 8-K filing on the award and its press release lean into that positioning, and the federal award record, NSF Award ID 2435244, is auditable.
ERASE is one of five additional teams NSF added to NQVL through its latest design competition round. The other four, per NSF's announcement, are working on different modalities: trapped-ion, neutral-atom, photonic, and other superconducting architectures. Dual-rail erasure is therefore not the federal bet on fault tolerance; it is one of several parallel bets, each small in dollar terms, each trying to show that its hardware-level mechanism can lower the error-correction tax enough to be the architecture that scales. The grant reads as a vote of confidence in the mechanism, not a verdict that the mechanism has won.
It is worth being honest about the scale. $1.57 million is incremental federal capital, the kind of seed grant that funds a two-year implementation phase rather than a build-out. A separate $100 million figure sometimes attached to D-Wave, tied to U.S. CHIPS Act funding for domestic quantum manufacturing, remains a Letter of Intent, not an executed award, and the company's own materials describe it that way. ERASE Phase II is a research milestone, not a commercial product. Real fault-tolerant advantage, if it comes from this line of work, is years away and contingent on dual-rail erasure surviving its first real benchmarks.
The watch items are concrete. Researchers will be looking for whether Quantum Circuits' hardware can hold erasure-flag fidelity over thousands of cycles, whether the dynamic-circuit operations ERASE plans to use can run on the available control stack, and whether the project's decoder-overhead numbers translate to outside labs. The first peer-reviewed hardware results from the consortium, and any D-Wave quarterly disclosure that ties ERASE milestones to commercial roadmap language, are the next signals worth tracking.