HWNEWS
HBM is the stacked DRAM next to AI accelerators. HBM4 lets customers redesign its base die, and the real squeeze is on design teams, not wafer supply.
High-bandwidth memory (HBM), the stacked DRAM that sits next to AI accelerators, is going custom. HBM4, the latest generation, is the first to let a customer design the bottom logic die of the stack, and that single capability has reordered who designs, who manufactures, and who assembles AI-grade memory. Micron, Samsung, and SK Hynix still own the DRAM, but the base die has shifted to a TSMC-class logic foundry on a finFET node (4nm or beyond), and the design seat is now contested between memory makers, hyperscalers, and XPU teams.
The custom variant, called cHBM, replaces the standard base die with a workload-tuned logic die. The HBM4 base die moved from a DRAM process to a logic process for power and performance reasons: up through HBM3, the base die used the same process as the DRAM itself. That move alone explains why the foundry column on the deal matrix now belongs to a TSMC-class fab, not the memory makers' own lines. Memory makers still handle assembly, dicing, and test of the final stack. What changed is who owns the silicon at the bottom of the stack and whose process it runs on.
The economic engine behind custom HBM is differentiation, not extra supply. Hyperscalers running custom XPU programs (custom CPUs, GPUs, and NPUs) want memory whose base die speaks the language of their accelerator. "How do I differentiate? One of the ways to differentiate is the cHBM model," said Rob Kruger of Synopsys, framing cHBM as a way for memory buyers to tune the stack to their chip rather than buy a generic commodity (Semiengineering). The wire will tell readers that cHBM exists. Memory buyers are paying for differentiation, not capacity.
Cross-domain design teams are the actual constraint. The scarce resource for cHBM is not wafer supply but engineers who can write a logic die that talks to both a memory stack and a customer's accelerator IP. Memory makers have the most stacked-DRAM experience. Hyperscalers have the most workload knowledge. Foundries have the process and the IP libraries. The negotiation among them decides who gets a custom stack versus a standard one, and that negotiation is happening project by project.
HBM supply is tight right now, but cHBM is not expected to further stress that demand. The standard HBM4 base die is being manufactured in volumes that compete with other advanced-node products, and the custom variant runs on the same advanced-node lines. The squeeze shows up in the design pipeline, not in the fab pipeline (Semiengineering).
Who designs the custom base die, who fabricates it, and who assembles the final stack: that trinity is the unanswered question of the HBM4 cycle, and the answer is per-deal, not industry-wide. Watch the first hyperscaler cHBM announcement. The matrix it reveals will be the template for the next five years of AI memory supply chains.