Nvidia has a $1 trillion backlog and a CPO roadmap for 2028. The chip that makes it possible is yielding 60-65% — meaning 35-40% of every wafer is scrap. The power wall is real. The fix is real. The manufacturing is not proven yet.
image from grok
Co-packaged optics promises a 70% reduction in link power for AI data center networks, but TSMC's COUPE process—the leading integration candidate—is achieving only 60-65% yield in early production, with roughly 35-40% of each wafer producing unusable parts due to photonic structure sensitivity. The manufacturing challenges stem from ring resonators, grating couplers, and thermal crosstalk that are inherently more variable than standard digital logic. As copper interconnects approach their practical limits at 3.2-terabit speeds, resolving these yield issues has become critical for hyperscalers seeking to address the fact that roughly 60% of data center energy is spent on data movement rather than compute.
The Grace Blackwell NVL72, a 120-kilowatt machine that Nvidia calls a single AI accelerator, is more precisely a copper greenhouse. Inside the rack, miles of cables connect 72 GPUs across 36 nodes, and the physics of moving data that far, that fast, generates enough heat to require dedicated cooling infrastructure. The NVL72 is not unusual. It is a preview of what every hyperscale AI training cluster looks like if nothing changes.
The industry knows this. The solution it is betting on is called co-packaged optics, or CPO, and the pitch is straightforward: move the optical transmitters from the edges of the rack to the chip package itself, reduce the power required to move data between GPUs, and eliminate a bottleneck that currently consumes a large fraction of a modern AI chip's total power budget. Nvidia's own analysis shows that transitioning from pluggable transceivers to CPO in 1.6-terabit networks can cut link power from 30 watts to 9 watts. The numbers are real. The problem is the chip that enables them does not exist in usable quantities yet.
Co-packaged optics replaces the separate optical transceiver modules sitting on the front of a switch with optical interfaces integrated directly into the chip package. The physical proximity eliminates the long electrical traces that drive power consumption up and bandwidth down. At 1.6 terabits per second and beyond, the alternative is running copper cables that dissipate tens of watts per port across distances that were never designed for that kind of throughput. The NVL72's copper backplane works because Nvidia has optimized the topology specifically for it. For general-purpose AI clusters at 3.2-terabit speeds, copper is running out of road.
Several foundries reported yields under 70 percent as of early 2026, according to Semiconductor Engineering's coverage of the CPO manufacturing challenge. TSMC's COUPE process, the leading candidate for high-volume CPO integration, targeted 60 to 65 percent yield in early production, implying that roughly 35 to 40 percent of each wafer produces parts that cannot ship. The difference from standard digital processes is not node maturity alone. COUPE integrates photonic structures — ring resonators, grating couplers, edge couplers — that are inherently sensitive to manufacturing variation in ways that standard logic is not. Each ring resonator heater consumes approximately 1 to 10 milliwatts, and thermal crosstalk between thousands of them on a single die creates yield challenges that digital circuits do not have.
About 60 percent of data center energy is spent on data movement, not compute, according to an analysis by SiliconAngle cited by Siemens' semiconductor packaging blog. I/O power can account for 50 percent or more of total chip power at AI training scale. If CPO can cut that in half, the power wall recedes. If the yield does not improve, the power wall stays where it is and the industry scrambles for copper solutions that will not scale to 3.2 terabits.
Nvidia knows both paths. At GTC 2026, CEO Jensen Huang disclosed that Nvidia's backlog grew from $500 billion to $1 trillion in one year, driven by inference demand that is doubling AI compute requirements annually, according to Semiconductor Engineering. Nvidia has invested $2 billion in Lumentum and an additional $2 billion in Coherent — total of $4 billion — to secure manufacturing capacity for optical interconnects, according to Futuriom. Separately, Nvidia announced plans to introduce a CPO-based Feynman rack-scale system in 2028. That roadmap is plausible only if COUPE yields improve. If they do not, the 2028 date moves, and Nvidia falls back on copper — which works today but has a documented scaling problem at the speeds AI training requires.
Broadcom has also signaled CPO deployment plans for 2027 and 2028. The timing is not coincidental. Sales of lasers and photonic integrated circuits for optical transceivers are expected to grow from $2.4 billion in 2023 to $5.9 billion by 2029, driven largely by AI data center demand, according to market research firm LightCounting cited in the Siemens blog. Hyperscalers are not spec'ing CPO because it is elegant. They are spec'ing it because the alternative is building larger clusters with more copper, more power, and more cooling infrastructure that the grid cannot necessarily provide. AI data center power demand is projected to grow 50 percent by 2027 globally, according to Goldman Sachs research cited in the same Siemens analysis. That growth rate, not the technology, is the constraint.
At OFC 2026, the optical networking industry's largest conference, Meta shared updated reliability data comparing CPO and pluggable optical transceivers at scale-out switch volumes, according to Semiconductor Engineering's OFC coverage. Meta's conclusion: CPO, at least the implementation evaluated, is more reliable than pluggable optical transceivers. That is a meaningful data point because CPO integration creates a longer replacement cycle — if the optics are co-packaged with the compute, a failure means replacing a more expensive unit. Reliability must be demonstrably better to justify the integration. Meta's conclusion, if it holds at scale, suggests the reliability concern is manageable. It does not resolve the yield concern.
The 3.2-terabit generation is where the copper-versus-optical debate becomes a physical argument rather than an engineering preference. At those speeds, electrical signaling across more than a few centimeters requires retimers at both ends of every link, adding latency, cost, and additional power draw. Optical avoids the tradeoff but requires photonic integrated circuits that can be manufactured at acceptable yields and tested at wafer scale. As of early 2026, that capability is in production at low volumes and under development at high volumes. The gap between low-volume and high-volume yields for photonic integrated circuits is not well-publicized because the companies doing the work do not have incentive to publish it.
By 2029, 3.2T ports are expected to exceed 10 million units annually, according to industry projections cited in the Siemens blog. The AI optics total addressable market is projected to exceed $20 billion per year by 2030, according to Network World coverage of OFC 2026. These are large numbers attached to a real problem. They are also contingent on COUPE yield climbing from the 60-65 percent range to something closer to what standard foundry processes achieve at maturity. If that improvement stalls, the projections will need revision, and the hyperscalers will need to find more power somewhere else.
The uncomfortable question for the industry is not whether CPO will work. The physics says it will. The question is whether photonic integration can yield at 80, 90, or 95 percent before the copper-based alternative runs out of road. TSMC has not published COUPE yield targets beyond early production. The next public signal will be when systems actually ship with CPO inside — not in a lab, not in a benchmark, but in a customer data center drawing 120 kilowatts and running training workloads. Until then, every projection in this article should be read with the understanding that the enabling technology has a 35 to 40 percent scrap rate and no backup plan if it does not improve.
Story entered the newsroom
Assigned to reporter
Research completed — 7 sources registered. CPO yield crisis: TSMC COUPE targeting 60-65% yield (35-40% scrap) as foundries report sub-70% yields in early 2026. This is the bottleneck nobody is
Draft (1150 words)
Reporter revised draft based on fact-check feedback
Reporter revised draft (1152 words)
Reporter revised draft (1156 words)
Reporter revised draft (1156 words)
Approved for publication
Published (1156 words)
Get the best frontier systems analysis delivered weekly. No spam, no fluff.
Space & Aerospace · 4h 27m ago · 2 min read
Space & Aerospace · 5h 48m ago · 2 min read
