Optical data links are moving from the edge of the circuit board into the chip package, and the manufacturing flow built around copper is being asked to handle light, heat, and a new class of defects.
The chip industry has decided it needs light inside the package. The manufacturing workflow has not caught up, and the cost of that gap, measured after final assembly, is a complete write-off of every good electrical component already committed to the job.
The reframe the industry is reaching for is to move optical test upstream, so a failed photonics engine forfeits no more than a single work-in-progress substrate rather than an entire assembled package. That is the lever named across a conference-synthesis feature in Semiconductor Engineering drawing on talks at the ECTC and IMAPS packaging conferences this spring. The story is not that integrated photonics has suddenly become easy. It is that system-level bandwidth and energy economics have made it unavoidable, and the process flow, designed when optics sat at the edge of the printed circuit board, is being asked to handle a different problem.
The shift is forced by economics, not novelty. Photonics, the use of light rather than electrical signals to move data on and off chips, is moving into the package and onto the chip because the cost of leaving the optical engine at the board's edge has become uneconomic at AI and data-center scale. ASE CEO Tien Wu said at ECTC that the industry is shipping silicon photonics in volume this year and that the next 20 years will be spent making the methodology, architectural design, and automated process more efficient, as Semiconductor Engineering reports. Wu argued the next wave will be 10 times the data-center and high-performance computing roadmap, and that no single company or region can do it alone.
A different set of constraints shows up once light is integrated into the package. Thermal load becomes load-bearing: the application-specific integrated circuit (ASIC) sitting next to the optical path is a heat source, and the optical path is sensitive to it. Lam Research's Prahalad Parthangal, quoted in the same Semiconductor Engineering feature, explained that temperature shifts change the refractive index (the way the material bends light) along the optical path, which drives insertion loss (the loss of signal strength as light moves through the assembly), and that thermal management will be needed at multiple layers and locations, not just one. Synopsys' Amlendu Shekhar Choubey made the same point from a design-tools angle: photonics is very sensitive to heat, so optical and electrical simulation have to coexist, with components co-designed from architecture through sign-off.
The structural and chemical problems look different in this regime, too. Larger and thinner packages warp when dissimilar materials expand at different rates, and the optical path cannot tolerate that distortion. Cleanliness moves from a nuisance concern to a functional one: a particle in a micro-lens cavity or residue at a bonding interface is now a defective optical engine, not a cosmetic defect. Brewer Science's Hamed Derami, also in the Semiconductor Engineering feature, put the chemistry in concrete terms: a single molecular layer of polymer on a pad can change how solder wets, which changes electrical performance, delamination (layers separating), and breakage, and propagates through everything else. Amkor's Suresh Jayaraman summarized the manufacturing state this way: it is not that integrated photonics has suddenly become manufacturable, it is that performance requirements are driving the transition, and the industry is scrambling to get there. Optical elements do not behave like normal die, he added, and the industry has to develop not just the process but the expertise to do it.
The architectural conversation is shifting in parallel. Nvidia's Sandeep Razdan, presenting at iMAPS, argued that what drives performance today is not really the number of floating-point operations, but the system architecture and system performance as a whole, a framing the Semiconductor Engineering feature ties to the case for co-packaged optics. Co-packaged optics, the practice of placing the optical engine a few millimeters from the ASIC instead of at the board edge, shortens the high-speed electrical path and reduces the signal-integrity burden, though the precise gain is architecture- and generation-dependent.
Two manufacturing paths are drawing the most attention. Nanoimprint lithography, which stamps repeating nanoscale patterns rather than exposing them with deep ultraviolet (DUV) light, has reappeared as a possible photonic patterning option. Chinese startup Prinano reportedly validated 200mm photonic-chip wafer production using nanoimprint instead of DUV, as Semiconductor Engineering reports, though the article itself flags that the claim is hard to evaluate without yield or defect-density data, and the figure should be read as a self-reported milestone rather than a verified production capability. Japan's National Institute of Advanced Industrial Science and Technology (AIST) presented a different path at ECTC, through researcher Fumi Nakamura, embedding photonic ICs in an organic substrate with single-mode polymer waveguides as an optical redistribution layer between the photonic chip and the optical connector, an attempt to make photonic integration compatible with established packaging processes.
The honest summary from the conference record is that the integration challenges are well-understood, named, and unresolved. The lever the industry is now pulling is the test flow, and the question for tool vendors, integrators, and the design side is what an upstream optical-test workflow needs to detect, from thermal drift to coupling loss to insertion loss, to convert a post-assembly write-off into a decision made in time. That is the work the next phase of the photonics build-out will turn on.