HWBRIEF
SPARC audits a chip design, before fabrication, for power leaks where a chip's power pattern betrays secret cryptographic state, and traces each leak to the exact software instruction.
A University of Lübeck team has built SPARC, a pre-silicon debugging framework that locates and root-causes power-side-channel leakage in processor designs before fabrication. (Note: the framework is unrelated to the long-running Sun/Oracle SPARC processor architecture.)
Power-side-channel leakage is a class of attack where a chip's power-consumption pattern betrays secret cryptographic state. Catching it is usually a post-silicon lab job, where a fix means a re-spin that can run into the millions of dollars. SPARC moves the audit earlier.
The mechanism pairs macro-cell-level Information Flow Tracking (IFT) with "shadow logic" that tags switching activity tied to secret-dependent data. Statistical leakage tests then identify which hardware signals are leaking, and the framework maps each of those signals back to the specific software instruction that triggered it.
The team, Andrija Nešković, Christian Ewert, Mladen Berekovic, and Saleh Mulhem, evaluated SPARC on AES and CRYSTALS-Kyber-512 (ML-KEM) running on a RISC-V target, both standard cryptographic workloads. The paper, "SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow," has been accepted at IEEE/ACM ICCAD 2026 in San Jose (November 8–12, 2026) and is on arXiv as 2607.23218v1 with DOI 10.1145/3831252.3834007. Semiconductor Engineering's Linda Christensen has a technical write-up dated July 28, 2026.
The full arXiv preprint describes the detection method but does not surface headline detection-rate or false-positive numbers; readers who need those should pull the preprint before betting the design flow on the framework's accuracy.