HWNEWS
Cerebras's new CS 4 AI server doubles inference tokens per user (the units an AI model reads and writes) at roughly the same cost as CS 3, by feeding more power to the same 5 nanometer process wafer (a single processor cut from a full silicon disc,
Cerebras builds AI accelerators the size of an entire silicon wafer. The company's newest rack, CS-4, doubles inference tokens per user over the prior CS-3 at roughly the same hardware cost, according to a SemiAnalysis deep-dive on the announcement. The chip did not change.
CS-4 is built around the same third-generation 5nm WSE-3 wafer-scale engine that powers CS-3. A wafer-scale engine is a single processor cut from a full silicon wafer rather than broken into smaller dies; in Cerebras's case, the chip carries 44 GB of on-chip SRAM, a kind of fast memory that sits next to the compute cores. Both the die and the memory budget are unchanged from the previous generation. Cerebras's product page and investor release frame the system as "up to 30 times faster than GPU-based solutions," but the public materials do not specify which GPU or workload generated that comparison, so the marketing number should be treated as a company-issued ceiling rather than a peer-reviewed benchmark.
Cerebras doubled per-wafer performance by feeding more power to the same WSE-3 die. CS-4 raises the wattage delivered to the wafer, the rack absorbs the extra heat, and the wafer runs faster as a result. Memory bandwidth doubles, and peak theoretical FLOPs double with it, per SemiAnalysis. The rack around the chip is also redesigned for modularity, which the company says shortens deployment time. The die is the same; the rack around it is not.
For inference workloads whose models fit inside 44 GB, the doubling is real and immediate. For workloads that need to host larger models on-wafer, the ceiling is exactly where it was a year ago. SRAM is fast but expensive, and the WSE-3's bit-cell count caps how much of it a single wafer can hold. Doubling the clock does not add a byte of memory.
CS-4 also doubles off-wafer bandwidth and introduces an open I/O module that lets the wafer hand work to HBM-based systems. Off-wafer I/O rises from 1.2 Tb/s on CS-3 to 2.4 Tb/s on CS-4. HBM, or high-bandwidth memory, is the stacked DRAM used in conventional AI GPUs. By letting CS-4 disaggregate inference across its own wafer and an attached HBM pool, Cerebras is conceding that the path past the 44 GB ceiling is no longer inside the wafer. It is next to it.
The company's own materials lead with the 2x and 30x speedup numbers. The GlobeNewswire distribution of the Cerebras release is the source of the "up to 30x" claim, and Cerebras's investor relations release repeats it. Neither pairs the speed number with a named GPU, a benchmark suite, or a model size. Hot Chips, the annual industry conference where chip companies present full technical details, is the next public window for the system.
CS-4 is a thermal and electrical repackaging of WSE-3, not a generational silicon leap. Doubled tokens per dollar is a real procurement story for inference buyers whose models fit. The architecture's capacity limit, and the open I/O module that is supposed to carry the architecture past it, are the parts of the announcement most likely to age well, and the parts Hot Chips is most likely to test.