The French high performance computing integrator, owned by Atos, has signed a memorandum of understanding with Alice & Bob to install cat qubit processors, quantum chips that suppress a class of errors at the chip level, in sovereign data centers across France, the UK, and…
Bull, the Atos-owned French systems integrator, has signed a memorandum of understanding with quantum hardware maker Alice & Bob to install cat-qubit processors inside European high-performance computing centers. Cat qubits are superconducting quantum chips engineered to suppress a class of hardware errors at the chip level. The deal is more than a partnership announcement: it is the first tier-1 HPC integrator to publicly stake production credibility on the bet that quantum's real bottleneck is not smarter error-correcting software, but the raw number of physical qubits needed to correct errors at all.
In conventional quantum hardware, errors arrive in two flavors. Bit-flips swap a qubit's 0 and 1; phase-flips corrupt the relationship between qubits. Standard quantum error correction handles both, but at a punishing cost: each useful "logical" qubit may require hundreds or thousands of physical qubits dedicated to detecting and correcting mistakes. Cat qubits, named for Schrödinger's cat paradox, are engineered so that bit-flips are dramatically rarer than in typical superconducting designs. The pitch is that, with bit-flip overhead collapsed, the engineering problem shrinks to managing the phase-flip errors that remain.
That pitch comes with a specific number. Alice & Bob claims its architecture can reduce the physical-qubit count needed for a given logical-qubit error-correction job by "up to 200x" compared with surface-code-style alternatives. It is the company's own benchmark framing, not an independently verified figure, and the comparison is against one specific approach rather than the full field.
The company has publicly reported progress consistent with the bit-flip suppression story. A 2023 arXiv preprint documented bit-flip times exceeding ten seconds for individual cat qubits, an unusually long window for a superconducting design. Quantum Zeitgeist reported in September 2025 that Alice & Bob had reached hour-long bit-flip resistance, framed as on-track for the company's 2030 large-scale quantum roadmap.
What Bull brings is not a quantum chip but the surrounding machinery: the sequencer electronics, the cryogenic and cooling integration, the data-center deployment, and the HPC system stack that a cat-qubit processor has to live inside to be useful. Bull's press release describes the partnership as targeting large-scale hybrid acceleration. Bull is positioned as the integrator, not as a co-developer of the underlying silicon. The MoU is also exactly that: a memorandum of understanding, not a deployed product, not a delivery contract, and not a customer announcement.
The geographic frame is part of the story. According to industry coverage of the partnership, the hybrid installations will target sovereign data centers in France, the United Kingdom, and Germany, a deliberate on-premises posture rather than consumption of public-cloud quantum services. For European industrial and government workloads with data-residency and sovereignty constraints, this matters: the public-cloud quantum providers are mostly American, and a domestic deployment option has strategic value independent of the underlying bit-rate.
Alice & Bob's most recent shipped system provides some scale context. In June 2026, the company delivered Helium, its first on-premises cat-qubit platform, with an 18-physical-qubit configuration marketed as the first premise-based cat-qubit system. That count refers to physical qubits on the chip, not encoded logical qubits; some coverage blurred that distinction. Bull's MoU is not tied to Helium specifically, and the integration pathway from an 18-physical-qubit box to anything resembling an HPC-grade hybrid accelerator will require substantial scaling.
The honest way to read this is as a directional bet, not a turning point. The cat-qubit advantage is bit-flip-specific. Phase-flip errors still need to be corrected, and the question is whether they dominate on the workloads HPC users actually want to run, including chemistry simulation, optimization, and machine learning kernels, at the scales a hybrid architecture would eventually address. If phase-flips dominate, the 200x figure looks generous. If bit-flips were the binding constraint, the figure understates the practical savings.
The arXiv bit-flip result is consistent with the suppression story, but it is a preprint, not peer-reviewed consensus, and it does not test a full error-corrected logical qubit. The hour-long resistance figure comes from the company itself, via industry coverage. Independent benchmarks on logical-qubit error rates under realistic workloads are the missing piece.
What to watch next: whether the MoU converts into a named deployment contract with a specific European HPC site, whether Bull's sequencer and cryogenic integration work reaches a published reference design, and whether Alice & Bob publishes logical-qubit performance data, not just bit-flip times, on systems larger than Helium. Until then, Bull's signature is a vote of confidence, not a result.