Beyond Bandwidth: The Industry is Striving for Custom Memory (Part 2)

The HBM4 spec is officially here, but the memory industry isn't waiting around. Multiple companies are now pushing custom memory solutions that go beyond what the standard promises — and they're doing it without throwing JEDEC compliance out the window.

In Part 1, we covered HBM4's 2,048-bit interface and massive bandwidth. But for AI accelerators that need even more capacity and efficiency, the next wave of custom memory is about squeezing more out of the stack without proprietary DRAM devices.

Marvell's Bet on Custom HBM4E

Marvell is leading the charge with what it's calling a custom HBM4E architecture that replaces the traditional 2,048-bit HBM4 PHY with a proprietary 32-GT/s 512-bit bidirectional die-to-die (D2D) interface. The key move: relocating the memory controller into a custom base die sitting beneath the DRAM stack.

"We want to leverage all of the work already done by JEDEC on DRAM stacking," Khurran Malik, senior director of product marketing for CXL, custom HBM, memory, and storage products at Marvell Technology told EE Times. "From the DRAM stack perspective, it remains JEDEC-compliant. The DRAM [device] stack is standard HBM4E. The customization happens in the base die and in the interface to the compute die."

The DRAM devices themselves stay JEDEC-standard — meaning Marvell's clients aren't locked into proprietary memory from a single vendor. That's a big deal because custom memory solutions historically meant buying entire stacks from one supplier, which gets expensive fast.

According to Nidish Kamath, director of product management for silicon IP at Rambus, the industry is moving toward this model: "What changes is the way the base die communicates with the host, which could be either proprietary or standards-based. This separation helps maintain supply chain stability while enabling differentiation at the logic level."

The Numbers

Marvell's pitch isn't just architectural — it's quantified. The company claims:

Up to 25% SoC area savings by removing the standard 2,048-bit PHY from the compute die

45-70% reduction in memory I/O power depending on the scenario

33% increase in memory capacity supported by the SoC

Higher peak bandwidth than standard HBM4E when stacking multiple custom modules

At the physical layer, the D2D link runs at 64 GT/s per wire bidirectionally (32 GT/s each way), delivering over 30 Tb/s/mm of bandwidth density when implemented on 2-nm or 3-nm class nodes. Marvell says that's considerably higher than current-generation UCIe links.

The IP includes lane redundancy with automatic repair, ECC, and RAS capabilities, plus adaptive power control that tracks bursty traffic. However, the company isn't disclosing the exact signaling or coding methods — standard practice when competitive advantage is at stake.

What's Still Unknown

This is where honest reporting matters. We don't yet know:

When these custom designs ship in volume

Which AI accelerators will first adopt the technology

Independent validation of the 45-70% power reduction claims

Malik declined to specify how many customers are developing XPUs with the proprietary D2D interface or active projects involving accelerators in the base die.

Why This Matters

The bigger trend here is the industry splitting into two layers: standardized DRAM stacks handled by memory vendors, and differentiated logic in the base die handled by accelerator designers. Marvell's approach proves you can push performance without breaking the supply chain.

As AI workloads demand more memory capacity closer to compute, expect more players to follow this playbook — keeping the DRAM standard, but owning everything above it.

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Part 1 of this series covered HBM4 fundamentals and the JEDEC standard specifications.

This article synthesizes reporting from EE Times with verification against primary sources including Marvell and Rambus.

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This article synthesizes EE Times reporting by Anton Shilov on custom HBM4E memory solutions, with verification against primary sources including Marvell and Rambus. Open claims about timelines and independent validation were clearly marked as unconfirmed.