Altera and Riverlane publish an open-source wiring standard for quantum error correction

Altera and Riverlane have validated an open wiring standard that moves error-correction data between a quantum computer's control electronics and the physical decoder chips that fix its errors in real time. The protocol, called the Quantum Error Correction Interface (QECi), is the missing plumbing layer for fault-tolerant quantum computing: syndrome data, the constant stream of error measurements from the qubits, has to cross from the control stack to the decoder in microseconds, or the correction cycle falls behind.

Riverlane has joined Altera's Solutions Acceleration Partner (ASAP) program and confirmed that QECi runs on Altera's Agilex 7 FPGAs, programmable chips that handle high-speed I/O. The Agilex 7 F-Tile transceivers route syndrome data with deterministic timing, and the validated reference design is now public on Riverlane's GitHub, with an Altera-specific path showing which Quartus toolchain version the team tested. Quantum hardware developers on superconducting, trapped-ion, or silicon spin-qubit platforms can now fork the design instead of wiring their own.

The partnership also covers Altera's Agilex 9 Direct RF FPGAs, which integrate data converters running up to 64 Gsps across a 36 GHz analog range, useful for connecting qubits to control and decoder logic without a separate analog front end. Altera's separate September 8 announcement added native post-quantum cryptography to its Agilex 3 and Agilex 5 lines, hardening long-life devices against harvest-now-decrypt-later attacks. The two pushes are parallel, not the same product: QECi is for the quantum stack, PQC is for classical systems that need to stay encrypted against future codebreakers.