HWNEWS
Alberta researchers showed AI chip placement models were training on the wrong metric, and a new approach that learns from whether the finished chip meets its speed budget beats the old way by 22% on worst case timing margin.
For years, the AI chip-placement field has trained its models on a fast, cheap estimate of total wire length. A new paper from the University of Alberta shows that estimate has near-zero correlation with the metric the industry actually ships, and that every AI placer the authors benchmarked lost to a decades-old baseline as a result.
Chip placement is the early stage of physical design where engineers decide where transistors and wiring blocks sit on a piece of silicon. A bad placement costs real speed, power, and silicon area on the finished chip, which is why machine-learning researchers have spent years trying to automate it. The standard training target across that work is half-perimeter wirelength (HPWL), a quick estimate of how much wire the placement would require. HPWL is fast and easy to compute, so the entire field has used it as a proxy for the outcome engineers actually care about: whether the routed chip meets its timing budget.
In arXiv 2608.13790, Chen and Han report that proxy is broken. Across ten circuits and four design flow stages, they measured the correlation between HPWL and the post-route timing metrics that predict whether a finished chip hits its performance target. The correlation was near zero. Every one of the six AI chip placers the authors benchmarked, when measured on post-route power, performance, and area, did worse than a hierarchical baseline that predates the modern machine-learning era. The architecture was not the problem; the labels were.
The authors' fix, packaged as PPAPlace, is to retrain on the right metric and let the timing signal flow all the way back to the placement step. They ran global routing on training examples to produce post-global-routing labels for worst negative slack (WNS) and total negative slack (TNS), the two standard ways engineers measure timing failures on a routed chip. A dual-stream model then learns from those labels: a graph-attention network reads the chip's wiring graph, a spatial-convolution network reads the placement grid, and a differentiable surrogate pushes timing gradients end-to-end back to the coordinates of every cell.
Two deployment modes come out of that setup. PPAPlace-CoOpt injects the timing signal into an analytical placer's optimization loop. PPAPlace-Refine takes an already-placed design and uses projected gradient descent to nudge macro positions until timing improves. The same trained predictor runs in both modes, with no test-circuit retraining.
On five ChiPBench circuits held out from training, the result is a 22% average improvement in worst negative slack and a 51% average improvement in total negative slack over the hierarchical baseline, with power and routability preserved. The SemiEngineering write-up frames those numbers as the constructive turn, and the code release makes the result reproducible.
The result is narrower than the headline number. Five test circuits is not a foundry validation; arXiv 2608.13790 is a preprint, not peer-reviewed work; and the authors do not claim their method generalizes beyond the benchmark they measured. Post-global-routing labels also still require running global routing per training example, which has its own compute cost the paper does not quantify. The method is one stage of one design flow on one benchmark family, and the field-level claim is a benchmark claim until industrial tape-outs confirm it.
The architecture arms race in AI chip placement has been running on a training target that does not predict the finished outcome. The PPAPlace result shows the diagnostic is correct and that switching the labels, with the right differentiable plumbing, is enough to flip the headline from "AI loses to the baseline" to "AI beats the baseline by a wide margin." The next move is to measure what you ship.