AI Won't Replace Chip Engineers. It Will Replace Their Workflows.

The software that designs the chips in your phone, your car, and your data center is being rebuilt around AI. The engineers using it aren't going anywhere. They are staying exactly where mistakes are hardest to catch.

Two of the largest chip-design software makers, Siemens EDA and Synopsys, now describe the same boundary in the same place. AI is taking over the parts of the chip-design workflow where errors are cheap to catch in a verification run. Humans are keeping the part where a misread paragraph of a specification can send a tape-out down a path no test plan will catch.

The mechanism behind the shift is what Siemens EDA's Abhi Kolpekwar and Synopsys's Ramesh Narayanaswamy call "callable engines." Where chip-design software used to be a monolithic tool the engineer drove step by step, it is being unbundled into smaller pieces: placement, routing, simulation, and test-plan generation. An AI agent can call them in sequence. The engineer manages the agents rather than clicking through the tool.

That is a structural change, not a feature add. Narayanaswamy describes a "sub-agent" pattern: a spec-analysis agent decomposes the chip's requirements, a test-plan agent turns that into verification scaffolding, and a critique model challenges the output. The human reviews the package, but the work is being done in parallel by machines the engineer is supervising.

Where the human stays in the loop is the question that decides what the new workflow looks like. Both executives point to the same place: the specification.

"There is significant talk of AI reading a specification and producing test plans, code, or formal properties," Kolpekwar told Semiconductor Engineering. "But the risk and cost of failure make adoption of fully autonomous spec-to-artifact generation unlikely for realistic semiconductor devices."

The reason is the verification asymmetry. A placement bug shows up in a tool log. A simulation miss shows up in a regression run. A specification misread, by contrast, produces a chip that does the wrong thing in exactly the way the wrong document told it to. The test plan, written to that same document, will not catch it. Verification only fails if it is verifying the wrong thing.

Narayanaswamy put it directly: the human must stay in the loop near the specification, because "if you misinterpreted a paragraph, you misinterpreted a paragraph." There is no cheap cross-check for a spec interpretation. The reviewer has to read it.

This is also why Kolpekwar rejects the more aggressive predictions — the ones that say AI could collapse the EDA industry or let a small team design a leading-edge chip from a paragraph of English. The verifiable parts of the workflow can be delegated. The spec cannot, and most of what makes a chip good or bad is settled in the spec.

What changes for engineers is the shape of the job. The work shifts from running tools to managing the agents that run them, and from writing every line of test scaffolding to reviewing what the agents propose. Current methodology (RTL design, formal verification, coverage closure) does not disappear. It sits underneath the new layer, called more often and reviewed more carefully.

What changes for the EDA vendors is the business. Two paths are now open. The established players, Siemens and Synopsys, are building agents that hook into their own tools. Larger chipmakers are building their own agents on top of the same engines. If the second path wins, the agent layer becomes the product and the EDA suite becomes plumbing. If the first path wins, the agents ship with the suite and the relationship is preserved. Both executives treat the split as a real business question, not a marketing one.

The watch item is narrow. Look for the first time a top-tier chipmaker publicly describes a tape-out where an AI agent wrote a non-trivial portion of the test plan or the formal properties, with the spec interpretation still human-supervised. That is the boundary Kolpekwar and Narayanaswamy are staking. If a major chipmaker reports a clean tape-out with a smaller human team than the comparable chip two nodes ago, the boundary has moved.

For now, the engineers are not going. The tools are.