AI Trained on Masked Chip Geometry Repairs 97% of Sub-2nm Rule Violations

A new framework from NVIDIA and Duke University, called SCALE, lifts state-of-the-art agents' solve rate on the smallest commercial chip designs to 97% on 100 real sub-2nm cases, a +12 to 25 percentage-point jump over prior systems. The gain comes from a specific two-stage learning move: teach a model to reconstruct masked chip-layout geometry from context, then turn that learned geometry sense into a design-rule repairer validated against a real foundry signoff checker.

The work, described in Semiconductor Engineering's trade summary, appears as arXiv preprint 2607.21850, an 8-page, 5-figure, 6-table text available in full at arXiv:2607.21850v1, submitted July 23, 2026, by a team spanning NVIDIA's Electronic Design Automation research group and Duke University: Ho, Yang, Zhou, Nishi, Li, Turner, Yu, Chen, and Khailany. The trade write-up positions it as a bridge between LLM-style chip-design scripting and the precise visual reasoning that layout work demands, a lane where general-purpose vision models fall short on foundry-specific geometry.

Sub-2nm here means the smallest commercial process nodes now in development, where the metal wiring layers that connect transistors are packed so tightly that design-rule violations, geometry errors a foundry's rulebook will reject at signoff, are no longer caught by a quick visual scan. Today's repair loop is mostly human: a designer sees a flagged spacing, width, or enclosure error, then nudges polygons around to satisfy the rule without breaking neighboring ones. At sub-2nm, that loop is the choke point.

SCALE's first stage treats chip layouts as a language. The system serializes the multi-layer wiring geometry on the back end of the line, the BEOL stack, into structured text, then asks a fine-tuned language model to reconstruct randomly masked polygons from their surrounding context. No violation labels are used in pretraining; the model only learns what legal local geometry looks like. The second stage exploits that learned sense: natural-language rule statements plus high-temperature sampling produce violation-prone layout variants, which an industrial signoff design-rule checker grades. The checker-graded pairs then fine-tune a domain-specific vision-language model, a DRC-VLM, that proposes concrete repairs for flagged violations.

On a benchmark of 100 real sub-2nm cases spanning enclosure, spacing, width, and color-spacing violations, the pipeline boosts prior agents' solve rate by 12 to 25%, with a top solve rate of 97%. The lift is consistent across violation types rather than carried by a single category, the authors report, and the repaired layouts pass the same industrial signoff checker that generated the training signal.

SCALE is a research preprint, not a shipped product. The 97% number is the authors' own evaluation on their 100-case benchmark, not an independent foundry or third-party run. The system is rule-aware and foundry-validated end-to-end, which is the point: it is being inserted into the existing rules-based repair slot, not replacing the foundry rule system or the chip designers who own the broader layout. As NVIDIA's EDA Research page frames the surrounding work, the lab's bet is on language-model-driven tooling that augments the existing pipeline rather than redesigns it.

That placement is why the result matters. Sub-2nm rule repair is the part of chip design where human iteration is hitting a geometry wall, and where a tool that proposes a foundry-valid repair in one shot changes the engineering-time budget. SCALE's two-stage move, geometry first, rules through a real signoff checker, is the specific bet on how to insert machine vision into that loop without losing the rule-aware discipline that signoff requires.