HWNEWS
Copper is hitting its physical ceiling inside AI clusters.
The racks inside an AI data center are wired together with copper, and the copper is running out of physical room. As cluster sizes grow, copper's reach shrinks, power draw climbs, and signal integrity degrades. Optical interconnects, chips that move data with light rather than electricity, used to be a niche. They are now scaling up.
That is the subtext behind STMicroelectronics' move into high-volume production of its PIC100 silicon photonics platform at the company's Crolles, France fab. The chips are built on 300-mm wafers, the same scale used for advanced logic and memory. Production is live, and ST says it plans to more than quadruple output by 2027, backed by long-term customer reservations rather than speculative capacity (ST press release).
The 300-mm line matters because silicon photonics has lived, until recently, on 200-mm fabs designed for older analog and mixed-signal parts. Tower Semiconductor has significant photonics capacity, but it is largely on 200-mm and heavily booked. TSMC offers silicon photonics, but access is not always easy. ST is positioning its 300-mm platform as a volume-capable alternative, the kind of capacity that lets a hyperscaler plan a multi-year optical roadmap without negotiating wafer starts like a foundry slot. PIC100 supports 100-GBaud signaling for 200G-per-lane applications, the building block for 800G and 1.6T transceivers, and the company is already working on a PIC100 variant with through-silicon vias (TSVs) to support Near-Packaged Optics (NPO) and eventually Co-Packaged Optics (CPO) (EE Times).
Sylvie Gellida, who runs ST's optical and RF foundry business, has been on this road for about a decade. The company built an earlier PIC25 platform at 50G per lane and reached production before the market was ready. R&D continued while the business was on hold. "The killer application wasn't there," Gellida said, describing the early-2010s pause. Now, she says, the planets are aligned: the AI build-out, the demand for higher-bandwidth optical links, and the engineering maturity to ship them at industrial scale. The bet is paying off because the application finally arrived (EE Times).
The packaging ladder matters. Today, pluggable transceivers, the modules that slot into the front of a switch, are the largest near-term market. NPO, where the optical engine sits next to the switch ASIC on the same board, is the next step. CPO, where the optics are bonded directly onto the package, comes later, once reliability and serviceability questions are answered. The CPO caveat is real. A failed pluggable module gets swapped; a failed optical engine bonded onto a switch ASIC is a different kind of problem. ST's roadmap tracks this stepped migration, with the TSV variant designed to make NPO and eventually CPO practical (EE Times).
A working signal came from Berlin-based Sicoya at OFC 2026 (March 15-19), where the company demonstrated a PIC100-based 1.6T-DR8 OSFP optical module: eight lanes at 200G per lane, with the transimpedance amplifier, the chip that converts weak optical signals back into electrical ones, die-stacked on the photonic chip. Eight lanes at 200G is what a next-generation switch port looks like, and the demo showed the platform can carry that bandwidth in a form factor that fits an OSFP cage (EE Times).
The market math, attributed to LightCounting via the ST press release, sketches the scale: the data center pluggable optics market reached $15.5B in 2025 and is projected to surpass $34B by 2030 (17% CAGR). Within that, LightCounting expects CPO alone to contribute more than $9B by 2030, and the share of transceivers using silicon photonics modulators to rise from 43% in 2025 to 76% in 2030. Those are third-party analyst projections, not shipped volume, and the press release cites them as the basis for ST's capacity build-out (ST press release).
ST is bundling the platform with its BiCMOS analog processes (for laser drivers and the electrical ICs the optical engine needs), its STM32 microcontrollers (for module control), and its packaging and test capability. The pitch is a one-stop shop for optical interconnect building blocks, the kind of vertical integration that lets a customer buy an entire optical engine from one supplier rather than assemble a bill of materials across four. The waveguide loss numbers ST claims for PIC100, 0.4 dB/cm on silicon and 0.5 dB/cm on silicon nitride, are company-reported and not independently measured, but they sit in the range the industry expects from a mature 300-mm silicon photonics process (EE Times).
The strongest counterargument to calling the transition inevitable is the one ST itself names: CPO's reliability and serviceability are not solved. Copper could also improve, with new cable materials and signaling schemes extending its reach. TSMC and Tower remain credible alternatives. The direction is clear, but the timing is not, and the next two years will sort out which foundries, packaging approaches, and module vendors actually carry the load.
The next concrete milestone is execution: ST's capacity expansion from current production to roughly four times that by 2027, the first NPO designs using the PIC100 TSV variant, and any CPO reference designs that survive a real hyperscaler qualification cycle.