AI's New Bottleneck Is the Power Bill

Two senior European research executives are putting a name on the constraint they say will define the next phase of AI infrastructure: not the transistor, but the system that surrounds it.

At Leti Innovation Days 2026, Jean-René Lèquepeys, CTO and deputy CEO of French state research institute CEA-Leti, told EE Times that scaling up AI systems now requires a full redesign, or they become "too costly and unsustainable from an energy standpoint." His German counterpart echoed the same conclusion: chip-level miniaturization still cuts energy use per transistor, but at the system level "significant further steps are needed to solve the energy problem."

Lèquepeys framed the work ahead as three engineering bottlenecks, each tied to the same wall. The first is delivering electricity efficiently to dense compute. The second is moving data between chips and across a rack with less energy per bit. The third is removing heat from systems that may run continuously at high utilization, where conventional air cooling can no longer keep up. None of these is solved by a smaller transistor.

Lèquepeys went on the record with the cost stack: electricity bills, costly accelerators, expensive cooling, and power-conversion hardware all compounding. "The mechanisms for viability are not really in place," he said, and added that the surprise of the past year was "the speed at which data centers became a central semiconductor use case," a market shift that arrived before the supporting engineering caught up.

AI is pushing software into every class of device, from edge inference boxes to high-bandwidth training clusters, he said, and the physical limits of where microelectronics can be deployed are now being felt. "Data centers cannot keep scaling unless microelectronic systems reduce their power demand," he warned, because cooling loads rise with compute capacity.

The industry term for the response is system-technology co-optimization, or STCO, an imec-coined phrase for treating power delivery, interconnect, packaging, and cooling as a single design problem rather than four separate ones. Siemens's 2026 outlook describes the shift as a move from "chip-first" to "system-first" thinking, with advanced packaging, chiplets, and 3D integration as the physical lever.

For hyperscalers and the construction firms that build for them, the cost of a gigawatt-scale AI site is now driven less by the accelerators inside it than by the electricity, transformers, pumps, heat exchangers, and optical interconnect around them. Lèquepeys's warning that the economic model is fragile is the same point, made from the research side.

Several concrete programs are pointed at the three bottlenecks Lèquepeys named. On power delivery, CEA-Leti has shown a new DC-DC converter technology that improves efficiency and opens a path to transformerless piezoelectric converters, a way to step voltage down on-chip or on-package with less wasted energy. On data movement, an EU-backed project has demonstrated a 100 Gb/s silicon photonics transceiver module, a candidate replacement for the copper and pluggable optics that dominate AI rack-to-rack links. On heat, researchers are revisiting microLEDs as both a potential optical interconnect medium and a way to move signaling off the most thermally constrained parts of a chip.

The next concrete test is whether the power-conversion, photonics, and packaging prototypes coming out of CEA-Leti and FMD move from lab demos to fab-scale integration in 2026, and whether the data-center buildout pipeline waits for them or outruns them.