AI's Memory Wall Is Forcing Chips to Stack Vertically

AI models keep outgrowing the memory that feeds them, and the next constraint is no longer raw compute. It is how much data can sit next to the processor, how fast that data can move, and how much energy it takes to move it. Pascal Vivet, who runs advanced programs at French microelectronics research institute CEA-Leti, told EE Times that the industry's current answer, high-bandwidth memory (HBM, stacked DRAM placed beside the processor), has hit a physical ceiling. "HBM means high bandwidth, but it's not wide enough," he said.

Leti's response is to place memory directly above the compute engine and redesign the interface around it. Vivet calls the design target "slower, wider, closer": trade raw interface speed for much wider buses, kept as physically close to the logic as possible. He said AI systems will need memory capacities "in the hundreds of gigabytes and possibly into the terabyte range" integrated close to the chip, "within the next few years."

Inference is the workload that exposes the ceiling first. Models repeatedly read the same weights from memory, so every read costs energy and time. Wider buses shorten the read; closer placement cuts the energy per bit. That is the physical case for stacking memory above the die rather than beside it, and it is the case Leti is using to position itself as a 3D integration toolbox inside an open chiplet ecosystem.

In April 2026, the institute demonstrated die-to-wafer hybrid bonding at 1 μm pitch (the spacing between bonded connection points), reported by Semiconductor Digest as one of the tightest pitches publicly disclosed for this class of assembly. In February 2026, Leti demonstrated what it described as the first dynamically routed electro-optical router for photonic interposers, a layer that uses light rather than copper to move data between chiplets. Both are slated for ECTC 2026, the industry's main packaging conference, where Leti will present its roadmap publicly.

The "open ecosystem" framing is the business pitch. Leti is positioning itself as a 3D integration toolbox inside an open chiplet ecosystem, a place where foundries, memory vendors, and system companies can test how to partition a chip into chiplets and bond them together. When memory sits above logic, the bonding pitch, thermal budget, and yield of the stack become the product itself.

The engineering difficulty is the test. Hybrid bonding at 1 μm pitch means aligning two wafers to within a micron of each other across the full wafer surface, then fusing them without trapping defects that would kill yield. Photonic interposers add a different failure mode: light paths that have to be aligned precisely enough for the optical interfaces to survive bonding. Stacking memory on top of a hot logic die forces a thermal budget current packaging tools were not designed for. Leti says it has solved enough of these to put them in front of ECTC reviewers. Whether the demos survive contact with volume manufacturing is the open question.

What to watch at ECTC 2026 is whether other foundries and memory vendors show competing pitches and thermal strategies, and whether "slower, wider, closer" shows up in any partner roadmap beyond Leti's slides.