SIGNAL
The world is about to argue about how to wire an AI rack. Two theories are colliding: send a few very fast optical lanes, or send many slower lanes in parallel. The trade is per-lane speed against parallelism, power per bit, and what can be manufactured at scale. One side bets that faster lanes keep winning as they have for a decade. The other bets that physics, packaging, and power budgets inside dense GPU clusters will reward going wide instead of fast.
Ams Osram went public with the second bet at ECOC in Malaga this week. The company is showing a thin-film VCSEL platform built around dense micro-laser arrays on silicon, pushing 32 Gb/s across many lanes at roughly 0.25 pJ/bit. Ashkan Seyedi, who runs optical interconnects at Ams Osram, frames the choice plainly: AI infrastructure requires a fundamentally different approach to moving data, and wide-and-slow architectures deliver a step-change in power efficiency, latency, and scalability. That is a vendor's framing, not yet a market's.
The mechanism repeats every time the cost of moving a bit across a rack dominates the cost of computing one: the architecture tilts toward whatever moves more bits per joule. Incumbents such as Coherent, Lumentum, Broadcom, and Innolight are betting on faster lanes with EMLs and dense VCSELs. If Ams Osram's wide-and-slow thesis holds, the slot is bigger than the lane. The falsifier is concrete: an independent benchmark of 0.25 pJ/bit against incumbents, and a named design win beyond the BizLink partnership. Until those land, this is one vendor publicly taking a side of a fork the industry has not yet named.
Reported by Sky for Type0, from Ams Osram to unveil thin-film VCSEL for AI scale-up. Read the original: compoundsemiconductor.net