AINEWS
Qualcomm, Google, and Meta are all rebuilding around RISC V, the open chip instruction standard, because AI model companies, not silicon vendors, are now setting the chip roadmap.
A 20-person startup in Shenzhen shipped a custom CPU two months after the first conversation. The team had never built that processor before. Five years ago, the same team could not have shipped it at all.
The team is SunRisc, a 2022 chip-design house founded by Zeng Yi, a 20-year semiconductor veteran. The custom CPU is a Domain-Specific Architecture (DSA), a processor built for one workload, in this case an AI inference target. Its two-month design cycle is the cleanest live signal that the chip industry's traditional design barrier has collapsed, and that AI is now writing the roadmap.
"AI changes the architecture decision," Zeng said in an interview with Lei Feng Wang (雷峰网). "The person who decides what a chip looks like is no longer the chip company. It is the AI model company."
The shift is visible in big-tech balance sheets. In December 2025, Qualcomm announced its acquisition of Ventana Micro Systems, deepening its RISC-V CPU portfolio. Google has been deploying SiFive's RISC-V Intelligence X280 inside its AI compute fleet, working alongside its in-house TPU. Meta's next-generation MTIA, the silicon behind its recommendation and inference workloads, is built on RISC-V. And in June 2026, The Register reported Qualcomm was circling AI-chip startup Tenstorrent in a deal said to be worth around $10 billion, a RISC-V power play if it closes.
RISC-V, the open instruction-set architecture maintained by RISC-V International and free to license and extend, is the de facto chassis of this shift. Closed ISAs, x86 owned by Intel and AMD, and ARM licensed by Arm Ltd, cannot be customized fast enough for model-specific silicon. A model needs a matrix-multiply engine, or a memory layout that matches its attention pattern. RISC-V lets a design house add those instructions. x86 and ARM do not.
Google began building around SiFive RISC-V cores in 2022 for AI infrastructure work, and Wired has tracked the broader wave of custom silicon that has followed. The pattern is the same: open ISA, custom extensions, AI workload in mind.
In China, RISC-V is splitting into two paths. The first is server-class RISC-V, with high visibility and ambitious roadmaps but slow commercialization. The second is DSA, the path SunRisc is on, where processors are built for one inference or signal-processing target. That path is already shipping. Zeng said the Shenzhen and Greater Bay Area market has moved en masse from ARM to RISC-V at the edge and in IoT, where short design cycles and customization matter more than peak per-core performance.
Zeng positioned SunRisc as the "Claude Code" or "Copilot" for chip design: a tool that uses AI to help a customer auto-generate a DSA processor. The framing is the founder's own. The underlying mechanic, AI-assisted design, is what makes a 20-person team competitive. The verification question is whether the AI tooling actually cuts engineering cost across a broader workload mix, or only at the prototype stage. SunRisc has not published that data.
The counterweight sits in Zeng's own caveat: RISC-V's server-side commercialization is still slow. The big-tech bets in 2025 and 2026 are R&D and acquisition moves; revenue from RISC-V server parts remains a fraction of the x86 and ARM installed base. SunRisc's bet is that DSA, not general-purpose server CPUs, is where the open standard actually eats first.
The next data point is the Qualcomm-Tenstorrent deal, reportedly still in negotiation as of June 2026. A close would harden the RISC-V server bet. An end to the talks would harden the DSA-first reading.