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The split between an AI model's reading and writing stages is pulling chip vendors into two camps, and Nvidia's $20B Groq bet is the loudest signal that one silicon no longer fits both jobs.
For years, the same kind of chip handled both jobs in the same box. The industry has now stopped pretending that works at production scale. "Disaggregated inference" is the term for what comes next: run the reading on one kind of silicon, the writing on another, and stitch them together with a fast network and a scheduler that knows what each stage needs. The shift is the first time chip buyers are being asked to pay for two accelerators per query instead of one.
The argument for splitting is economic. The reading stage eats FLOPS, the writing stage eats memory bandwidth, and a chip optimized for one leaves the other idle. Paying for general-purpose compute to handle both halves of the job is waste, and per-token economics now favor chips tuned for just one half. Cambrian-AI Research analyst Karl Freund makes the case in Forbes that the value is migrating from the chip itself to the compiler path, the scheduler, and the per-token economics, and that the market will reward specialization over generalization (Cambrian-AI Research, Forbes). Freund's firm discloses Nvidia and Cerebras, both named in the piece, as paying clients. The architectural argument stands on its own, but readers should know the analyst is not a neutral observer.
The deals landing in the last six months are the proof. Nvidia closed a roughly $20 billion acquisition of Groq's LPU IP, assets, and engineering team last December, the largest single bet that the writing stage needs its own silicon. The plan pairs Groq's language-processing units, which are tuned for low-latency, single-token generation, with Nvidia GPUs handling the heavy reading, all orchestrated by Nvidia's Dynamo software (Forbes). Groq's LPU is the inference startup's specialty: a deterministic, latency-pinned architecture aimed at the writing half of the pipeline.
A second camp is forming around AMD and Cerebras, with AWS Trainium available as a second prefill option alongside AMD's MI4xx GPUs. Cerebras's wafer-scale silicon is Ethernet-based and targets the writing stage the same way Groq's LPU does. AMD's MI4xx GPUs handle the reading stage, with Cerebras documenting the recipe in its own engineering blog (Cerebras blog) and AWS publishing both a developer guide and a launch post for its Neuron-based disaggregated inference stack (AWS Neuron NxD inference docs, AWS blog on llm-d).
Intel is positioning itself as the glue. At Computex 2026 the company demonstrated a live disaggregated inference stack using Xeon processors for orchestration and execution, Nvidia Blackwell GPUs for prefill, and SambaNova's RDUs for decode, the most public proof so far that the four major silicon vendors can sit inside one serving pipeline without one of them owning the whole box (Forbes).
Google's TPU is the open question. Freund argues that TPUs are tuned for Google's own training and serving traffic, which is a captive advantage inside Google Cloud, and that Google may eventually have to commercialize the chips more broadly to keep up with the disaggregation curve (SemiAnalysis on TPUv7). The TPUv7 generation is the first that analysts outside Google are reading as a serious inference option, not just a training accelerator.
Disaggregated inference is a cost story before it is a performance story, and the vendors that survive will be the ones whose schedulers turn idle silicon into billed tokens. Reading-stage chips compete on raw throughput per dollar; writing-stage chips compete on latency, determinism, and how cleanly they plug into someone else's network. Through 2027, AI hardware news will read as noise unless the reader has that frame: ask which half of the pipeline a new chip is built for, what the partner silicon is, and who is writing the scheduler.