AI data centers are going optical. The tools to test those chips can't talk to each other.

Silicon photonics is moving from research into mainstream chip design for AI infrastructure and data centers. The design side is largely solved. The verification side is not.

A photonic integrated circuit, a chip that routes data with light rather than electrons, can be laid out in a specialized design tool. Its electro-optical-electrical behavior, the part that decides whether the chip actually works inside a system, has to be checked in a separate simulator. That split is the bottleneck, and it is the story behind a recent Semiconductor Engineering feature on designing electro-optical chips.

The two environments do different jobs. The first draws waveguides, modulators, and detectors at the device level. The second models how phase, wavelength, polarization, and thermal drift will behave once that device is wired into a real workload. They speak different languages, and there is no shared ground truth between them. Designers call the result a handoff problem. As silicon photonics leaves the lab for data-center volume, it is starting to behave like a production-readiness problem with money, power, and interconnects on the line.

When a hyperscale data center ships an optical interconnect that fails, the cost is not the chip. It is the server, the rack, and the row of capacity around it. That is what turns the research-grade handoff into a volume-production problem, and it is why EDA vendors are the ones with the most to lose. Their customers, chip teams, foundry partners, and the hyperscalers buying the systems, will measure them on the seam, not the slide.

Photonic behavior is continuous and governed by Maxwell's equations, the same laws that describe electrical circuits but stretched across an extra dimension. The numerical methods used to solve them, finite-element modeling and finite-difference time-domain simulation, overlap with electronic design automation but each demands a deep specialization. EDA platforms built for transistor-level digital design have to extend into waveguides, optical phase, wavelength, polarization, thermal drift, and mechanical stress on a shared ground truth with the system-level simulator. The seam is where that extension work has to land.

Keysight EDA is one vendor trying to stretch. Niels Fache, the company's senior vice president for EDA, has framed the work as specialization on top of existing EDA infrastructure rather than a green-field stack. Cadence and Synopsys, the two largest EDA houses, are also working in the space; the trade-publication piece describes the broader industry context.

Laying out a photonic circuit is largely solved. Simulating its continuous physics, including compact models for waveguides and the thermal and mechanical drift that comes with them, is largely solved. Showing, on a shared ground truth, that the circuit behaves correctly when it is wired into a system-level electro-optical-electrical path, is not. AI-assisted workflows are starting to help, but they do not paper over the missing backbone. The piece calls functional verification the biggest unresolved gap in the stack.

Chip teams, EDA buyers, and infrastructure engineers should be putting one question to any vendor selling into this space: where is the shared simulation backbone across photonic design and EOE system verification, and how is continuous-physics functional verification actually handled? If a vendor can point to one, the gap closes on contact. If they cannot, the answer matters more than the roadmap slide.

The seam between the design tool and the system-level simulator is the bottleneck, and the next volume production cycle will be the one that exposes which EDA vendor has actually closed it.