AI Chips Are Getting Bigger. The Old Flatness Rules Can't Keep Up.

A substrate passes every flatness number on the bench. It still fails at bonding, alignment, or downstream yield, because the deformation lives at a different length scale than the spec was measuring.

That gap is the new front line of advanced packaging. As AI and high-performance computing chips grow larger, stack chiplets with high-bandwidth memory, and migrate to panel-scale substrates, the industry's habit of measuring package flatness as a single global bow number is breaking down. The replacement is process-aware: a discipline of tracking surface shape at every handoff and asking which shape components, from which process steps, are driving yield and reliability loss. A Semiconductor Engineering analysis of the issue traces the shift to several converging forces.

"Stop treating flatness as one global mechanical number," the source argued. Flatness is now a composition of length-scale signatures that come from the process itself, and that composition is what bonding, lithography, and reliability actually respond to.

Wafer-level packages are giving way to panel-level processing, where suppliers like ASE have automated lines handling 310mm × 310mm panels. Scaling up the area does not automatically scale up the physics. Coating uniformity, thermal stress, and mechanical stiffness all behave differently across a panel than across a 300mm wafer. Hybrid bonding, the technique that eliminates solder bumps by fusing copper pads directly through aligned oxide surfaces, is moving from research to production. There is no organic underfill to absorb mismatch at the interface, so the oxide surfaces must be essentially bone flat for the chemical bond to form. The copper recess and anneal steps introduce their own coefficient-of-thermal-expansion (CTE) mismatch that makes flatness process-specific rather than material-specific. A single particle or chemical-mechanical polishing (CMP) scratch can become a yield limiter.

Glass carriers and glass substrates are a partial response. The CTE of engineered glass can be tuned from roughly 3.4 to 10.6 parts per million per degree Celsius, and the material is stiffer, smoother, and optically transparent enough for laser or ultraviolet debonding. That buys headroom, but it does not resolve the underlying CTE imbalance inside a heterogeneous stack, where silicon chiplets, organic or glass interposers, and HBM dice expand and contract at different rates.

Engineers respond to that complexity with three broad strategies. The first is physical constraint: vacuum chucks, stiffener rings, and carrier frames that redistribute stress without removing it. The second is compensation: lithography exposure-field correction and pick-and-place offset, both of which require dense, repeated surface metrology to know what to correct. The third is structural: redesign the stack and thermal profile so the package is flat where it has to be flat, including at its operating temperature.

That last point is the one the source keeps returning to. "We used to design the package to be flat on the bench, then assume it would be fine in the field," the source said. "Now we design for the operating temperature" (typically 90 to 100°C or higher for HBM-equipped AI packages), "and the package can measure worse at room temperature on the bench and still be the better part." The implication is jarring for anyone used to bench inspection as a proxy for field behavior. A part that looks worse in metrology may be the one that survives in a server.

The cost of getting this wrong has gone up in step with panel scale. Panels loaded with chiplets and HBM can run into tens of thousands of dollars per unit, the source told Semiconductor Engineering, so a warpage yield problem that surfaces late in the build is now an expensive yield problem, not a bench-debate problem. The total thickness variation of the temporary bonding layer sets the lower limit on die-thinning uniformity, and that non-uniformity propagates downstream into every step that depends on a known die thickness.

Simulation is the missing connective tissue. The source noted that substrate suppliers treat their recipes and material formulations as competitive assets, so most warpage models rely on generic material libraries that are less precise at predicting real outcomes. Combined with metrology that is shifting from target-based point checks to repeated, high-density surface-shape measurement at every handoff, the field is converging on a discipline that looks more like process control than inspection.

Earlier metrology, better material data shared with simulation vendors, and stack designs that balance CTE and stress across heterogeneous layers are the constructive response. The package is not asked to be flatter. It is asked to be flat at 95°C, in shapes the metrology can measure and the simulation can predict.