A*STAR's FAPlace Placement Tool Resizes the Interposer as It Places Chiplets

2.5D advanced packaging lets chipmakers bolt several smaller "chiplets" side-by-side onto a silicon interposer inside one package, instead of carving the whole system out of one large die. Get the interposer size wrong and every downstream step has to bend around it.

FAPlace, a footprint-aware, mask-guided sequential placement framework from Singapore's ASTAR, breaks that loop. Today, designers pre-specify the interposer's footprint, then place chiplets inside it; if the layout comes out cramped or the wires too long, they resize and re-place. The ASTAR team instead runs the layout on a large canvas and lets the optimal interposer size emerge as an output, fusing area compactness, aspect-ratio control, wirelength, and thermal guidance into one deterministic pass via a footprint mask and supporting masks.

According to the abstract excerpt carried by Semiconductor Engineering, the tool reduces wirelength and footprint area, drives aspect ratios close to square, and holds thermal performance flat. The paper appears on pp. 942–947 of the GLSVLSI 2026 proceedings; a Creative Commons preprint is at arXiv 2607.02610.

What the abstract does not show: how FAPlace compares to commercial 2.5D place-and-route tools at production scale, what benchmark suite it was tested on, or whether the single-pass approach scales to designs with many more chiplets than the paper's experiments.