A single machine readable contract shared by hardware, firmware, and verification teams could shift correctness checks upstream of testing, but the tool chain to build one remains fragmented and prior attempts to standardize specs have not held.
The verification bottleneck in chip design, the months of simulation, formal checks, and coverage analysis that stand between a finished design and a tape-out, has long been treated as a problem of running more tests, or running them smarter. A growing cohort of specification engineers argues the real failure is further upstream, in the specification itself, which is typically written in prose and consumed separately by hardware, firmware, verification, and software teams before any chip code is committed.
That separation is where "spec drift" begins. Each team re-translates the document into its own working language: hardware engineers into the register-transfer-level design code that current chips are written in, firmware engineers into driver code, verification engineers into simulation testbenches, and now AI generators into modules that may or may not match what anyone else understood. No amount of downstream test coverage repairs that loss.
A small but vocal group of specification practitioners says the fix is to make the specification itself executable. A "golden specification," in their framing, is a single machine-readable artifact that hardware, firmware, software, and verification teams can each consume in their own dialect without lossy re-translation, and that AI agents can also read. Ashish Darbari, CEO of Axiomise, argues it must be "a living, machine-readable, executable artifact consumable by hardware, firmware, verification, and system teams without lossy re-translation," which is, he says, where spec drift begins. William Wang, CEO of ChipAgents, treats it as the AI-interpretable ground truth against which all generated hardware code, testbenches, and analyses are evaluated, and warns that "without such a reference, correctness becomes undefined."
The motivation is concrete. Wilson Research Group's annual functional verification study, published through Siemens EDA, has tracked first-time silicon success sliding for years as chip complexity outgrew verification throughput. Trade-press analysis in SemiEngineering and a Siemens EDA Verification Horizons post pin the same trend on system companies building increasingly heterogeneous chips where hardware, firmware, and software now share the correctness burden.
The major electronic-design-automation vendors have moved in lockstep. Cadence launched its ChipStack AI super agent as an explicit "AI-front-of-flow" play that ties chip design and verification behind one interface. Synopsys is rebranding its emulation and prototyping hardware as "Software-Defined Hardware-Assisted Verification", positioning decades-old silicon for AI-era workloads. Both companies reinforced that direction on their most recent earnings calls, with Cadence's Q4 2025 transcript and Synopsys's Q4 2025 transcript emphasizing AI-augmented verification as a strategic growth lane. The broader industry reframing frames these moves as part of a coordinated shift "left," toward earlier in the design flow, where fixing errors is cheaper.
The resistance is also concrete. The tool chain that would build, maintain, and consume a golden specification remains fragmented. Model-based systems engineering tools, requirements databases, verification management platforms, high-level synthesis engines, and the new generation of AI code and register-transfer-level generators exist as separate products that are still poorly wired together. Prior attempts to standardize at the register-map layer, including SystemRDL and IP-XACT, did not end spec drift; they simply relocated it. The "gold" in "golden specification" is precisely the unsolved part: getting hardware, firmware, software, and AI agents to consume one artifact in their own working languages, without lossy translation, is the problem that neither existing standards nor new vendor AI tooling has cracked.
If the framing holds, the stakes shift visibly. Time-to-sign-off is the obvious one: a chip that is correct by construction should tape out faster and cheaper. The less obvious one is accountability. Under the old model, verification engineers caught errors late, in simulation, in formal proofs, in coverage closure. Under a golden-spec model, the specification authors bear the cost of getting the contract right early, and the verification team becomes the auditor of a machine-checked translation rather than the last line of defense. That is a different organization, with different hiring, different metrics, and a different definition of who owns correctness.
What to watch next is whether any major electronic-design-automation vendor can ship a tool chain that actually links a written specification through to coverage closure, instead of treating each stage as a separate product. Cadence's ChipStack and Synopsys's software-defined emulation are early commitments, not finished flows. A buyer-side skeptic, a system company willing to say publicly that the golden-spec story is more vendor narrative than deployed workflow, has not yet surfaced. Until one does, the verification bottleneck will stay exactly where it has been for a decade: a problem everyone can describe and no one can buy a fix for.