A peer reviewed result on Processing using DRAM, memory chips that compute alongside storing data, is being read as a soft veto inside JEDEC, CXL (Compute Express Link) memory standard working groups, and hyperscaler procurement reviews.
A peer-reviewed 48% interference finding on memory chips that compute is doing institutional work before the first such chip ships at scale. The number is moving through JEDEC, CXL working groups, hyperscaler procurement reviews, and DRAM-vendor product councils as a portable lever against an architecture the AI industry has been counting on to cut data-movement costs.
The finding comes from a multi-institution team of researchers from the University of Tokyo, ETH Zurich, CISPA, and RIKEN, working under the paper nickname PuDGhost. Their target is a chip category called Processing-using-DRAM, or PuD, a flavor of in-memory computing in which ordinary dynamic random-access memory (DRAM) chips, the working memory in every server, are coaxed into doing arithmetic on the data they hold instead of just handing bits to a separate processor. The pitch is straightforward. If the memory can compute, the data never has to travel across the memory-to-processor bus, which is the dominant energy and time cost in modern AI training and large-data analytics. Dozens of academic and industrial processing-in-memory (PIM) efforts, from Samsung's HBM-PIM to UPMEM's CPU-attached DIMMs to a wave of CXL-attached memory devices, are built on that bet.
The PuDGhost team did not simulate it. They bought real DRAM chips, ran the relevant PuD operation on them, and measured what happened when neighboring circuitry was active at the same time. The headline number is this: when multiple DRAM columns compute concurrently under the simultaneous multiple-row activation (SiMRA) pattern, the result in any one column can be corrupted by up to 48%, depending on what data sits in non-activated rows and in the other columns. That envelope, not the "ghost" nickname, is the engineering story, and it is the artifact that has begun migrating out of the paper and into the surrounding institutional ecosystem.
What makes the 48% figure politically potent is not its severity in any single chip. It is its legibility. A number with a clean ceiling, a peer-reviewed methodology on real silicon, and a four-institution author roster can be dropped into a JEDEC comment, a CXL-PIM working group objection, a hyperscaler product security incident response team (PSIRT) review, or a DRAM-vendor product council agenda without anyone having to defend the underlying measurement. Standards-body participants can invoke the figure against PIM adoption without waiting for a regulator to act, much as the RowHammer bit-flip research migrated into DDR5 mitigation requirements over the past decade, but playing out in real time before commercial PuD chips reach production volume.
That trajectory is what separates this from a vulnerability disclosure. A CVE typically travels through coordinated disclosure, a vendor patch, and a public advisory before it acquires institutional weight. The PuDGhost finding has no patch to coordinate. The 48% envelope is a measurement of a physics-of-the-chip phenomenon, not an exploit, and the chip architecture it describes is not yet in customer hands at meaningful volume. There is no patch clock to honor. There is only a number, and the number is moving on its own.
The source basis is honest about what is and is not yet nailed down. The paper was surfaced through SemiEngineering's technical papers roundup on 22 June 2026. The 48% SiMRA interference figure is paper-reported on real DRAM chips rather than independently corroborated in a second lab at this stage, and the full author list and venue details should be confirmed against the upstream paper before being treated as settled. The mechanism, non-activated row data and concurrent-column data corrupting a PuD operation, is the part that is robust regardless of which exact figure survives scrutiny, and it is the part that gives procurement reviewers and standards-body participants something specific to design around or object to.
The watch items now sit in three places. First, JEDEC and CXL-PIM working groups will see whether the figure is invoked by name in upcoming comments and whether it lands in any next-generation PIM specification footnote. Second, hyperscaler accelerator procurement teams that had PIM on their roadmap will see whether the figure shows up in internal reliability and total-cost-of-ownership models alongside thermal and yield assumptions, a quiet insertion rather than a press release. Third, the DRAM vendors themselves, Samsung, SK hynix, and Micron, will see whether their own product-council responses treat the finding as a controllable reliability item to engineer around or as a strategic signal to slow the PIM roadmap. None of those moves require a regulator. The 48% number has already done the work to make them possible.