A 26×33mm Mask Ceiling Is Why Cars, Surgical Robots, and Humanoids Now Share Chip Blueprints

A lithography mask slightly larger than a postage stamp, 26 by 33 millimeters, caps how big any single chip can be printed in one exposure step. That physical ceiling, set inside the fab rather than on the marketing slide, is the engineering reason the same silicon building blocks are now being ported from car computers to surgical tools, water systems, and humanoid robots. A recent trade-press explainer branded this cross-industry convergence as "physical AI", a label that groups surgery, cars, water, and humanoids under one banner. The mechanism behind it is closer to a consequence than a category.

The chip industry's response to that ceiling is decomposition. Rather than build a single, ever-larger system-on-chip (SoC) for each new product, engineers stitch together smaller chiplets, each carrying a specific function such as compute, memory, or sensor input, and connect them inside one package. imec's Automotive Chiplet Program runs this approach for vehicles, and imec is now extending the playbook to a broader class of edge devices.

Inside the fab, the workaround for the field cap is reticle stitching, the process of printing a single die from multiple adjacent exposures. As feature sizes shrink to 5nm and below, chipmakers already rely on inverse lithography (ILT) and optical proximity correction (OPC) at their most critical layers. ILT is computationally heavy and produces long mask write times, but it generates the curved features that compensate for optical and process distortions across the exposure field. Applying ILT to stitching is the new step. It lets designers join separately patterned regions into one logical die while smoothing the seams where distortion would otherwise degrade yield.

imec's program pages frame the portability as deliberate: reference designs, packaging flows, and partner playbooks developed for ADAS, sensor fusion, and infotainment are now feeding the new Autonomous Edge Chiplet Program. Five members have joined recently: GlobalFoundries, Infineon, Silicon Box, STATS ChipPAC, and TIER IV, according to imec's announcement. The mix covers foundry capacity, power devices, advanced packaging, and an autonomous-driving stack builder, so the playbook is being adapted, not copied wholesale.

Hyperspectral imaging is already in use in surgery and disease diagnostics, and pilots are running for water conservation. Robotics and broader edge-AI workloads sit earlier in the chiplet program, with reference designs and pilot runs in place but few ship dates. Trade press coverage groups these as a single "physical AI" wave. The commercialization gap is real. Some of these blocks are in production now, while others are still on a chiplet program roadmap.

A 26×33mm mask and a curved-feature lithography technique are the units of portability. As long as the ceiling holds, every new device that needs more silicon than fits in a single exposure will borrow the same building blocks, whether it is bolted into a car, wheeled into an operating room, or perched on a robot.